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ML53812-2

H.100/H.110 CT Bus System Interface and

Time-Slot Interchange

January 2000

Revision HistorySeptember 1999January 2000320101-005320101-006Previous ReleaseTiming tables altered on page 50: “Local Clock and Frame Synchronization Timing”, “Local Clock to CT Bus Clock Skew”, and “Local Serial Stream Timing”Timing diagram (Figure 11) atered on page 51:“Local Clock and Frame Synchronization Timing”Oki Semiconductor

ContentsDescription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3ML53812-2 176-Pin LQFP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7CT Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Pin Continuity Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Analog PLL Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Analog PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Slave PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Master PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Reference Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Local Clock and Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Local Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10CT Bus Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11CT_D disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Diagnostic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11GPIO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Message Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Microprocessor Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Command/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Internal Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Device ID Registers (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Stream Switch Routing Registers, AR = 1007h:1000h (Ch. 7:0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Stream Switch Connection Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Transmit Switch Routing Registers, AR = 20ffh:2000h (Ch. 255:0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Receive Switch Routing Registers, AR = 30ffh:3000h (Ch. 255:0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Indirect Transmit Switch Parallel Access Registers, AR = 40ffh:4000h (Ch. 255:0) . . . . . . . . . . . . . . . . . . . 45Indirect Receive Switch Parallel Access Registers, AR = 50ffh:5000h (Ch. 255:0) . . . . . . . . . . . . . . . . . . . . 45Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47H.100/H.110 Bus Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Clock Skew Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56ML53812-2 Package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57LQFP176 Package Outlines and Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57LQFP176 Mounting Pad Reference Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Oki Semiconductor

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Oki Semiconductor

ML53812-2H.100/H.110CT Bus System Interface and Time Slot Interchange1.0 DESCRIPTION

The ML53812-2 is a complete CT Bus system interface and time slot interchange device that provides acost-effective connection between a computer board’s telephony interfaces or signal processing resourcesand the CT Bus. The ML53812-2 is an evolution of existing time-slot interchange ICs which offers seam-less interoperability with SCbus devices.

A key element in computer telephony (CT) equipment is the auxiliary telecom bus. Most manufacturersof high-capacity CT equipment have used one or more types of telecom buses to transport and switchlow-latency communications traffic between boards within the computer, bypassing the computer’smain I/O and memory buses. To simplify the integration of devices that incorporate a telecom bus, theEnterprise Computer Telephony Forum (ECTF) developed a standard bus (H.100/H.110 CT Bus™) thatprovides compatibility modes with the most prevalent telecom buses today (SCbus™ and MVIP-90™),as well as the capacity and feature set needed to support the next generation of high capacity CT servers.The new CT Bus is embraced by Dialogic under the Signal Computing System Architecture™ (SCSA™)umbrella of open standards for building interoperable CT systems.

The ML53812-2 runs in both 4 MHz and 8 MHz SCbus modes and supports the switching featuresneeded to integrate CT Bus devices with 4 MHz SCbus, 8 MHz SCbus, and 2 MHz MVIP-90 devices.Because the H.100/H.110 CT Bus uses an identical switching model and clock speeds to that used for theSCbus, developers have unparalleled flexibility in integrating these two types of devices, or in transition-ing from one type to the other.

The ML53812-2 takes full advantage of the mandatory and optional features defined in the ECTF H.100and H.110 interoperability specifications. It is a non-blocking 512 x 4096 time slot switch, interfacing upto 512 ports on its parent device to any of the 4096 time slots on the new CT Bus. The high number of localtime slots available makes it easier to design high-density CT hardware, supporting as many as eight net-work interfaces or 256 voice processing ports per chip.

This powerful chip is offered in an ultra slim profile (176-pin LQFP package, with a 24 mm x 24 mm x 1.4mm body size) that makes it possible to mount the chip on either side of the board. The chip is fully soft-ware programmable, and can be controlled by a variety of microprocessors, including Intel and Motorolain both multiplexed and nonmultiplexed modes.

Oki Semiconductor1

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2.0 FEATURES

•High functionality, low cost implementation of the ECTF H.100/H.110 interoperability specifications.

•Simple to connect PCI and cPCI™ board-level circuitry to the universally accepted CT Bus™.•Ultra slim profiling (176-pin LQFP package). •Up to 512 programmable connections (256 transmit and 256 receive) to any of the 4096 time slots on the H.100/H.110 CT Bus.

•8-channel stream-to-stream switching for data stream connections at variable rates.

•Implementation of all compatibility signals for complete interoperability with existing 4 MHz SCbus™, 8 MHz SCbus, 2 MHz MVIP-90™ devices, and H-MVIP™.

•Provides reliable clock synchronization for network-grade connection to digital network interfaces.

•Supports all H.100/H.110 CT Bus clock fallback features.

•Choice of constant or minimum switching delay on a per time slot basis.•3.3 V I/O with 5 V tolerant input.

•Supports multiplexed and nonmultiplexed address/data bus modes for both Intel and Motorola microprocessors.

•Supports CT Bus optional message channel interface, for both H.100 (PCI) and H.110 (cPCI) applications.

•Supports a variety of framing formats via a configurable local bus.

•Efficient microprocessor interface access to Local and CT Bus data streams through direct parallel access to/from transmit and receive switch.

2.1 Applications••••••

Low and high-density computer telephony hardware (PCI and cPCI platforms)Enhanced service platforms

Private branch exchanges (PBXs)Wireless base stations

Internet telephony systemsDigital trunking equipment

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3.0 PIN CONFIGURATION132131130129128127126125124123122121120119118117116115114113112111110109108107106105104103102101100999897969594939291908913313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517688878685848382818079787776757473727170696867666564636261605958575655545352515049484746451234567891011121314151617181920212223242526272829303132333435363738394041424344Figure 1. ML53812-2 176-Pin LQFP Pin ConﬁgurationOki Semiconductor3

3.1 ML53812-2 176-Pin LQFP Pin Assignment [1]Pin 1234567891011121314151617181920212223242526Pin NameVDDCALEVDDOCS_NRD_NWR_NVSSORESETI_NINTVDDOD_0A_0D_1A_1VSSOD_2A_2D_3A_3VDDOD_4A_4D_5A_5VSSOPin 2728293031323334353637383940414243444546474849505152Pin NameD_6A_6D_7A_7A_8A_9VDDOL_NETREF_0L_NETREF_1L_NETREF_2L_NETREF_3VSSOL_NETREF_4L_NETREF_5L_NETREF_6L_NETREF_7VSSCVDDCVDDOAPLL_VDDOAPLL_VDDCAPPL_PCAPPL_VCOAPPL_VSSCAPLL_VSSOPin 53545556575860616263646566676869707172737475767778Pin NameVSSOAPLL_TESTTMSTCKTRST_NTDITDOVDDOMC_TXDMC_RXDMC_CLKVSSOC16_NEG_NC16_POS_NVDDOC4_NC2VSSOSCLKX2_NSCLKVDDOFR_COMP_NCT_MCVSSOCT_C8_BPin 7981828384858687888990919293949596979899100101102103104Pin NameVDDOVSSOCT_NETREF_2CT_NETREF_1VDDOCT_C8_AVSSOVSSCVDDCCT_D_0VDDOCT_D_1CT_D_2VSSOCT_D_3CT_D_4VDDOCT_D_5VSSOCT_D_6VDDOCT_D_7CT_D_8VSSOPin 105107108109110111112114115116117118119120121122123124125126127128129130Pin NameCT_D_9CT_D_10VDDOCT_D_11VSSOCT_D_12CT_D_13VDDOCT_D_14VSSOCT_D_15CT_D_16VDDOCT_D_17CT_D_18VSSOCT_D_19VDDOCT_D_20VSSOCT_D_21CT_D_22VDDOCT_D_23CT_D_24VSSOPin 131132133134135136137138139140141142143144145146147148149150151152153154155156Pin NameCT_D_25VSSCVDDCCT_D_26VDDOCT_D_27VSSOCT_D_28CT_D_29VDDOCT_D_30CT_D_31VSSOGPIO_0GPIO_1VDDOGPIO_2GPIO_3VSSOL_SI_0L_SI_1L_SI_2L_SI_3VDDOL_SI_4L_SI_5Pin 157158159160161162163164165166167168169170171172173174175176Pin NameL_SI_6L_SI_7VSSOL_SO_0L_SO_1L_SO_2L_SO_3VDDOL_SO_4L_SO_5L_SO_6L_SO_7VSSOL_CLK_0L_FS_0L_CLK_1L_FS_1CT_D_DISABLETESTVSSCAPPL_CLKREF80CT_FRAME_B_N106NC 59CT_FRAME_A_N1131.In this document, signals ending with “_N” are “active low” (eg. CS_N). Note that in the H.100/H110 specification, active low is indicated with apreceding forward slash (eg. /CS).4Oki Semiconductor

4.0 SIGNAL DESCRIPTIONSSignal Description [1]NameD_[7:0]A_ [9:0]ALE (AS)CS_NRD_N (STRB_N)WR_N (R/W_N)RESETI_N (M)CT_D_DISABLEL_NETREF_[7:0]L_SI_[7:0]MC_TXDAPLL_CLKREFAPLL_VDDOAPLL_VDDCAPLL_PCAPLL_VCOAPLL_VSSCAPLL_VSSOAPLL_TEST TESTTMSTCKTRST_NTDIINTCT_D_[31:0]CT_FRAME_A_NCT_C8_A CT_NETREF_1CT_NETREF_2CT_FRAME_B_NCT_C8_BCT_MCDescriptionMicroprocessor Data Bus. (I/O, TTL Schmitt, 8 mA, 5V tolerant) Microprocessor Address Bus. (Input, TTL Schmitt, 5V tolerant)Intel Bus Mode - Address Latch Enable. Motorola Bus Mode - Address Strobe. The Microprocessor Address Bus A[9:0] is latchedinternally on the falling edge of this signal. (Input, TTL Schmitt, 5V tolerant)Chip Select. This active low signal selects the ML53812-2 for a microprocessor read or write operation. (Input, TTL Schmitt, 5Vtolerant)Intel Bus Mode - Microprocessor Bus Read. Motorola Bus Mode - Microprocessor Bus Strobe. (Input, TTL Schmitt, 5V tolerant)Intel Bus Mode - Microprocessor Bus Write. Motorola Bus Mode - Microprocessor Bus Read/Write signal. (Input, TTL Schmitt, 5V tolerant)Reset. This active high input signal initializes the microprocessor interface, configuration, and routing registers. (Input, TTLSchmitt, 5V tolerant)Microprocessor Bus Mode. When this input is low, Intel Bus Mode is selected. When this input is high, Motorola Bus Mode isselected. (Input, TTL Schmitt, 5V tolerant)CT_D Global disable. (I/O, TTL Schmitt, 8 mA, 50 k Pull Up, 5V tolerant)Local Network Reference [7:0] Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)Local bus Serial Input Data Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)Message Channel Transmit Data Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)Analog PLL Clock Reference Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)+3.3 Volt Analog PLL I/O Power Supply+3.3 Volt Analog PLL Core Power SupplyAnalog PLL Phase Comparator Analog OutputAnalog PLL VCO Analog InputAnalog PLL Core GroundAnalog PLL I/O GroundAnalog PLL Test Enable Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)Test Select. This input enables the pin continuity test. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)Test Access Port Mode Select. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)Test Access Port Clock. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)Test Access Port Reset. (active low). (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)Test Access Port Data Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)Interrupt Output. (I/O, TTL Schmitt, 50 k Pull Up, 8 mA, 5V tolerant)CT Bus Serial Data Streams. (I/O, PCI, 5V tolerant)CT Bus \"A\" Frame Sync. (I/O, TTL Schmitt, 24 mA, 5V tolerant)CT Bus \"A\" 8 MHz Clock. (I/O, TTL Schmitt, 24 mA, 5V tolerant)CT Bus Network Reference 1. (I/O, PCI, 5V tolerant)CT Bus Network Reference 2. (I/O, PCI, 5V tolerant)CT Bus \"B\" Frame Sync. (I/O, TTL Schmitt, 24 mA, 5V tolerant)CT Bus \"B\" 8 MHz Clock. (I/O, TTL Schmitt, 24 mA, 5V tolerant)CT Bus Message Channel. (I/O, TTL Schmitt, 24 mA, 5V tolerant)Oki Semiconductor5

Signal Description [1]NameFR_COMP_NSCLKSCLKX2_NC2C4_NC16_POS_NC16_NEG_NL_CLK_1L_FS_1L_CLK_0L_FS_0L_SO_[7:0]MC_CLKMC_RXDGPIO_[3:0]TDONCVDDOVSSOVDDCVSSCDescriptionCompatibility frame sync used by SCbus, MVIP-90, and H-MVIP. (I/O, TTL Schmitt, 24 mA, 5V tolerant)SCbus Clock. (I/O, TTL Schmitt, 24 mA, 5V tolerant)SCbus X2 Clock. (I/O, TTL Schmitt, 24 mA, 5V tolerant)MVIP-90 2.048 MHz Clock. (I/O, TTL Schmitt, 6 mA, 5V tolerant)MVIP-90 4.096 MHz Clock. (I/O, TTL Schmitt, 6 mA, 5V tolerant)H-MVIP 16.384 MHz Positive active low Clock. High to low transition on frame boundary. (I/O, TTL Schmitt, 24 mA, 5V tolerant)H-MVIP 16.384 MHz Negative active low Clock. Low to high transition on frame boundary. (I/O, TTL Schmitt, 24 mA, 5V tolerant)Local bus Clock 1. (I/O, TTL Schmitt, 24 mA, 50 k Pull Up, 5 V tolerant)Local bus Frame Sync 1. (I/O, TTL Schmitt, 24 mA, 50 k Pull Up, 5V tolerant)Local bus Clock 0. (I/O, TTL Schmitt, 24 mA, 50 k Pull Up, 5 V tolerant)Local bus Frame Sync 0. (I/O, TTL Schmitt, 50 k Pull Up, 24 mA, 5V tolerant)Local bus Serial Output Data Streams. (I/O, TTL Schmitt, 50 k Pull Up, 8 mA, 5V tolerant)Message Channel Clock Output. (I/O, TTL Schmitt, 50 k Pull Up, 6 mA, 5V tolerant)Message Channel Receive Data Output. (I/O, TTL Schmitt, 50 k Pull Up, 6 mA, 5V tolerant)General Purpose I/O ports. (I/O, TTL Schmitt, 24 mA, 50 k Pull Up, 5V tolerant)Test Access Port Data Output. (Output, 6 mA, 5V tolerant)No Connect+3.3 Volt I/O Power SupplyI/O Ground+3.3 Volt Core Power SupplyCore Ground1.Signals ending in “_N” are active low.6Oki Semiconductor

5.0 FUNCTIONAL DESCRIPTIONThe ML53812-2 has the following interfaces:••••Microprocessor InterfaceLocal Serial Data InLocal Serial Data OutLocal Timing•Analog PLL Reference Clock•CT Bus Timing •CT Bus Serial DataMicroprocessorInterfaceConfiguration & Routing RegisterInternal Control8 Channel Stream Switch256 x 4096 Transmit SwitchLocal ConnectLocal SerialData InCT Bus Serial DataLocal SerialData Out4352 x 256Receive SwitchInternal TimingSlave Digital PLLMaster Digital PLLAnalogPLL131.072 MHzCT Bus TimingLocal TimingAPLLReference ClockFigure 2. Block Diagram5.1 Local BusThe local bus consists of up to eight serial input ports and eight serial output ports, totalling 512 possiblelocal bus connections to the CT Bus. The input and output ports can be configured independently as twogroups of four 2 Mb/s streams, two 4 Mb/s streams, or one 8 Mb/s stream. The chip includes two inde-pendent, configurable local clock and frame synchronization signals. The local clocks have configurablepolarity and frequency that can be set to 2 MHz, 4 MHz, 8 MHz, or 16 MHz regardless of local streamdata rate. The local frame syncs also have a configurable polarity and can be set to use one of three fram-ing formats (early, straddle, or late).To transfer data to and from the local bus, the ML53812-2 allows the user to select a minimum delay orconstant delay buffer mode on a per channel basis. In the minimum delay mode, the input-output buffertransfer occurs on the next 2 Mb/s time slot boundary, reducing any potential channel delay for classicvoice processing applications. In the constant delay mode, the buffer transfer occurs at the frame bound-ary for bundling and proper switching of wide-band data, for data sent on the ISDN H channel.Oki Semiconductor7

5.2 CT Bus

The ML53812-2 provides access to all 4096 CT Bus time slots. The upper 16 data lines run at 8 Mb/s,while the lower 16 data lines can be configured, in groups of four, to run at 8 Mb/s, 4 Mb/s, or 2 Mb/sfor compatibility with SCbus and MVIP-90 devices.

The chip uses an internal analog phase locked loop (PLL) as a rate multiplier to produce a 131.072 MHzinternal clock locked to a variety of reference frequencies. This high frequency internal clock providesfine grained correction steps (7.6 nS) for the master and slave digital PLLs. The main CT Bus network ref-erence signal can be configured to run at 8 kHz, 1.544 MHz, or 2048 MHz. The timing for the CT Bus canbe configured to be derived from the local clock and frame sync signals to allow multiple chips to be con-nected to the CT Bus without overloading the reference clock line.

The ML53812-2 incorporates internal master digital PLL circuitry that is designed to meet the jitter atten-uation, holdover and Maximum Time Interval Error (MTIE) requirements of 62411 Stratum 3,4 and 4E.This enables the ML53812-2 to be well suited for developers of digital telephone network interfaces,where reliable clock synchronization is critical. Because the circuitry is internal, board designers do nothave to add expensive or custom circuitry to support these types of environments.

The ML53812-2 also includes an 8-channel stream-to-stream switch to connect one CT Bus data stream toanother at the same or different data rates. This type of connection makes it possible for CT Bus compat-ible devices (such as SCbus and MVIP-90) to efficiently exchange data even though they operate at differ-ent rates. This stream switch enables switching between any of the 32 CT Bus data streams operating at2, 4, or 8 Mb/s. Depending upon the data stream rates, the stream switch provides a minimum of 256 anda maximum of 1024 unidirectional time slot connections. Stream switches in other ML53812-2 devices,within a system, may be used simultaneously to increase switching capability.5.3 Test Access Port

The current version of the ML53812-2 does not support IEEE 1149.1 Boundary Scan. The Test Access Porton the ML53812-2 passes TDI through to TDO when TMS and TRST_N are both high which simplifiersthe transition to eventual Boundary Scan support. Drive TMS and TRST_N both low for normal opera-tion.

5.4 Pin Continuity Test

For normal operation, the TEST pin is driven low. When the TEST pin is high, all pins except VDD, VSS,NC, APLL_PC, APLL_VCO, TMS, TCK, TRST_N, TDI, TDO, TEST are sequentially \"NAND’ed\" withALE and output on TDO. This test allows each input pin to be toggled and a corresponding output to beobserved on the TDO pin to verify the proper connection of the ML53812-2 to a printed circuit board.5.5 Analog PLL Test

For normal operation, the APLL_TEST pin is driven low.5.6 Microprocessor Interface

Both Intel and Motorola microprocessor bus interfaces are supported. Drive I_N (M) low for Intel modeand high for Motorola mode. Multiplexed addresses are latched on the falling edge of ALE (AS). If mul-tiplexed address is not used, drive ALE (AS) high. Multiplexed address and data must be connected toboth A_ and D_ pins.

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5.7 Analog PLLThe analog PLL is used to create an internal 131.072 MHz clock locked to one of several reference fre-quencies. The analog PLL reference signal is input on the APLL_CLKREF pin and should be a stableclock typically ± 25 ppm. An external loop filter is required (see Figure 3).R2100ΩR119 kΩAPLL_PCCI0.01 µFAPLL_VCOAPLL_VSSFigure 3. Analog PLL Loop Filter5.8 Slave PLLThe slave PLL is used to generate all of the internal timing for the ML53812-2. Even when the ML53812-2 is enabled as master, the slave PLL is still in operation. The slave PLL is a fast tracking digital PLL oper-ating at 131.072 MHz.The slave PLL can be configured to lock to one of the following sources:••••••CT_C8_A and CT_FRAME_ACT_C8_B and CT_FRAME_BSCLK and FR_COMPC2 and FR_COMPL_CLK_0 and L_FS_0L_CLK_1 and L_FS_15.9 Master PLLThe master PLL is used to generate timing for the CT Bus. The master PLL is a digital PLL operating at131.072 MHz. When operating as primary master the PLL can lock to one of eight local network refer-ences, or one of two CT Bus network references. These reference signals may be 8 kHz, 1.536 MHz, 1.544MHz or 2.048 MHz. When operating as secondary master the PLL locks to the primary CT Bus master.The master PLL can be configured to automatically switch from secondary to primary in the event of aCT Bus timing error.The master PLL can be configured to drive either the CT Bus \"A\" or \"B\" signals as well as all of the com-patibility clocks defined in the H.100/H.110 Specifications.When operating as the primary master, the PLL provides jitter attenuation with a cut-off frequency of1.25 Hz and a roll-off of 20dB per decade. When operating as the secondary master, the PLL is fast track-ing.When operating as the primary master, the PLL has a lock range of ±488 ppm (minus the tolerance ofAPLL_CLKREF source). The maximum lock time is 3s. Holdover stability is 0.06 ppm, resulting in aframe slip rate of 42/day, assuming no drift in APLL_CLKREF source, exceeding the 62411 Stratum 3requirement of 255/day. During normal operation new holdover values are updated at 128ms intervals. Oki Semiconductor9

To make an MTIE compliant reference switch, enable \"Condition Master PLL referenceer PLL Referencehe selected reference.The following sequence will produce an MTIE-compliant reference switch:1.Change the \"Master PLL Mode\" from Normal to Holdover. The master PLL can also be configured tomake this change automatically in the event of a master PLL error. 2.Change the \"Master PLL Reference Select\" to the new reference, or change the reference source ofCT_NETREF.3.Change the \"Master PLL Mode\" back to Normal.MTIE SpecificationsML53812-2MTIE during rearrangementPhase change slope100 ns81 ns / 1.326 ms62411 Stratum 3 and 4E1 µs81 ns / 1.326 ms5.10 Reference MasterCT_NETREF_1 and CT_NETREF_2 can be independently configured to output a reference signal to theCT Bus selected from one of eight local network reference inputs. The local network references can bepassed through or divided by 192, 193, or 256.5.11 Local Clock and Frame SyncTwo sets of local clock and frame sync are provided. A variety of clock frequencies, polarities, and fram-ing formats may be selected to allow \"glue less\" local port interfacing. Each set of local clock and framesync may be configured separately. The frequency selection is independent of the local stream rate. 5.12 Local StreamsThe local streams consist of up to eight serial input ports and eight serial output ports, defined as twogroups of 128 time-slots. Each group can be independently configured to operate as four 2 Mb/s streams,two 4 Mb/s streams, or one 8 Mb/s stream. Local Stream Time Slot to Channel MappingLocal streamL_SI_0,L_SO_0L_SI_1,L_SO_1L_SI_2,L_SO_2L_SI_3,L_SO_3L_SI_4,L_SO_4L_SI_5,L_SO_5L_SI_6,L_SO_6L_SI_7,L_SO_78Mb/s stream rate time slot 127:0channel 127:0---channel 255:128---4Mb/s stream rate time slot 63:0channel 63:0channel 127:64--channel 191:128channel 255:192--2Mb/s stream rate time slot 31:0channel 31:0channel 63:32channel 95:64channel 127:96channel 159:128channel 191:160channel 223:192channel 255:22410Oki Semiconductor

5.13 CT Bus Streams

Connection to all 32 CT Bus streams is supported without restriction. The upper 16 streams run at 8Mb/swhile the lower 16 may be configured, in groups of four, to operate at 8Mb/s, 4Mb/s, or 2Mb/s.5.14 CT_D disable

The user may disable all CT_D output streams in the event of a bus timing error. When enabled, an erroron the slave PLL reference source causes the CT_D streams to be tri-stated until an entire frame timewithout errors has passed. The CT_D_DISABLE signal is provided to link multiple ML53812-2 devices.5.15 Diagnostic Mode

Diagnostic mode tri-states all CT Bus signals while internally looping-back CT Bus outputs to inputs.This mode allows a printed circuit board containing the ML53812-2 to be thoroughly tested withoutcausing CT Bus errors.5.16 Interrupts

The ML53812-2 supports the following interrupt sources:•CT Bus A Error•CT Bus B Error

CT Bus A (CT Bus B) error is detected when CT_C8_A (CT_C8_B) rising edge does not occur within35 ns of the expected time, relative to the previous period (see Figure 4) or when CT_FRAME_A_N(CT_FRAME_B_N) low does not occur when expected. (See ECTF H.100/H.110 Specifications fordetails on CT_C8_(A/B) and CT_FRAME_(A/B)_N signal timing.)•SCbus Error

SCbus error is detected when SCLK does not transition at close to the expected frequency (C_[25:24]determines the expected frequency) or FR_COMP_N low does not occur when expected. (See ECTFH.100/H.110 Specifications for details on SCLK, SCLKx2, and FR_COMP_N signal timing.)•MVIP Error

MVIP error is detected when C2 does not transition at close to 2 MHz, or FR_COMP_N low does notoccur when expected. (See ECTF H.100/H.110 Specifications for details on C2 and FR_COMP_N sig-nal timing).

•Master PLL Out of Lock Error

Master PLL error is detected when the master PLL is not locked to the selected Reference defined byC_[43:40].•Frame Boundary

Frame Boundary interrupt is not an error condition, and occurs when the internal state machinecrosses a frame boundary. •GPIO

GPIO interrupt occurs when one or more of the GPIO inputs match the programmed latch polarity,defined by C_[167:136].

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The interrupts are both globally and individually maskable, and are signaled to the processor via the INTpin (pin 10). The INT pin can be configured to operate as either push-pull or open drain, and its polarity(active high or active low) is also selectable. All of these interrupt latches have an individual enable/clear register and an individual interrupt maskregister associated with them.Rising edge of CT_C8 occurring after this limit will trigger an interrupt (if enabled).CT_C8_(A/B)Expected Delay (Approx. 125 ns)Late Allowance (35 ns)Figure 4. CT_C8_A and CT_C8_B Error Detection5.17 GPIO PortsFour general purpose input/output ports are provided. The ports may be individually configured to avariety of modes and can also be used as interrupt sources. Possible uses of the GPIO ports would be con-trolling H.100/H.110 termination switches or implementing the SCbus CLKFAIL signal.5.18 Message ChannelThe ML53812-2 provides a complete interface between the CT_MC CT Bus signal and a local HDLC con-troller. This includes generation of MC_CLK as well as buffering of MC_TXD and MC_RXD. 12Oki Semiconductor

6.0 REGISTERS6.1 Microprocessor Address MapWith Direct Parallel Access Disabled (C_[96] = 0) (Default)A_[2:0]7h6h5h4h3h2h1h0hReservedData Register 2 (DR_2)Data Register 1 (DR_1)Data Register 0 (DR_0)ReservedAddress Register 1 (AR_1)Address Register 0 (AR_0)Command/Status RegisterRegisterWith Direct Parallel Access Enabled (C_[96] = 1)A_[9:0]3FFh:300h2FFh:200h1FFh:008h007h006h005h004h003h002h001h000hDirect Receive Switch Parallel Access Ch. 255:0Direct Transmit Switch Parallel Access Ch. 255:0ReservedReservedData Register 2 (DR_2)Data Register 1 (DR_1)Data Register 0 (DR_0)ReservedAddress Register 1 (AR_1)Address Register 0 (AR_0)Command/Status RegisterRegisterOki Semiconductor13

6.2 Command/Status RegisterD_[7:0]01234567Busy (Read Only)Read Command (Write Only)Write Command (Write Only)Terminate Command (Write Only)ReservedReservedReservedReset (Read/Write)DefinitionBusy (D_0) (Read Only)This bit is set (\"1\") when a Command that requires synchronization with the ML53812-2's internal state machine has been initiated, and cleared (\"0\") when the command has been completed.For Commands that do not require synchronization this bit is always clear (\"0\").The following commands require synchronization:•Routing Memory Write command•In-Direct Parallel Access Read or Write commandRead (D_1) (Write Only)Setting this bit (\"1\") initiates a synchronized read of the register pointed to by the Address Register. When the Busy bit is clear (\"0\"), the contents of the register to be read are available by reading the Data Register. It is NOT necessary to clear (\"0\") this bit after it has been set (\"1\").Note: For \"Reads\" that do not require synchronization (all \"Reads\" except In-Direct Parallel Access Read) it is not necessary to set this bit. The Data Registers can be read immediately after writing the Address Register. Write (D_2) (Write Only)Setting this bit (\"1\") initiates a write of the register pointed to by the Address Register. It is NOT necessary to clear (\"0\") this bit after it has been set (\"1\").Terminate (D_3) (Write Only)Setting this bit (\"1\") terminates a command that requires synchronization with the ML53812-2's internal state machine. The command in process is completed asynchronously and the Busy bit is cleared. It is NOT necessary to clear (\"0\") this bit after it has been set (\"1\").Reset (D_7) (Read/Write)Setting this bit (\"1\") resets the ML53812-2 and initializes the Configuration and Routing Registers. This command is analogous to the function of the RESET pin. Clearing this bit (\"0\") returns the ML53812-2 to normal operation, ready to be configured.14Oki Semiconductor

6.3 Internal Address Map [1] [2]AR0014h:0000h00ffh:00fch1007h:1000h20ffh:2000h30ffh:3000h40ffh:4000h50ffh:5000hConfigurationDevice IDStream Switch Routing Ch. 7:0Transmit Switch Routing Ch. 255:0Receive Switch Routing Ch. 255:0Indirect Transmit Switch Parallel Access Ch. 255:0Indirect Receive Switch Parallel Access Ch. 255:0Register1.AR is the concatenation of AR_1 and AR_0.2.All other locations reserved (Read-back = 00, Write has no effect).Oki Semiconductor15

6.4 Configuration RegistersNote: All \"Reserved\" configuration registers should be written \"0\". Configuration Register Byte 0, AR = 0000hDR_00123[7:4]C0123[7:4]Diagnostic ModeTest ModeAPLL Power-down ModeAPLL Bypass ModeAPLL CLKREF Frequency [3:0]DefinitionDiagnostic Mode (C_ [0]) (Read/Write)Set to 0 for normal operation01→ → Diagnostic Mode DisabledDiagnostic Mode Enabled (Default)Test Mode (C_ [1]) (Read/Write)Enables testing with the slave DPLL bypassed. Set to 0 for normal operation.01→ → Test Mode Disabled (Default)Test Mode Enabled APLL Power-down Mode (C_ [2]) (Read/Write)Powers down analog PLL, resets APLL charge pump. Set to 0 for normal operation.01→ → APLL Power-down Mode DisabledAPLL Power-down Mode Enabled (Default)APLL Bypass Mode (C_ [3]) (Read/Write)APLL Bypass used during simulation and testing. Set to 0 for normal operation.01→ → APLL Bypass Mode DisabledAPLL Bypass Mode Enabled (Default)APLL CLKREF Frequency [3:0] (C_ [7:4]) (Read/Write) Put APLL in Power-down (C_[2] = 1) when changing APLL CLKREF Frequency.0h1h2h3h4h5h6h7h - fh→ → → → → → → → 65.536 MHz (32 X 2.048 MHz) (Default)49.152 MHz (24 X 2.048 MHz)32.768 MHz (16 X 2.048 MHz)16.384 MHz (8 X 2.048 MHz)8.192 MHz (4 X 2.048 MHz)4.096 MHz (2 X 2.048 MHz)2.048 MHzReserved16Oki Semiconductor

Configuration Register Byte 1, AR = 0001hDR_0[1:0]234567C[9:8]101112131415Slave Bus Mode [1:0]Slave Local Timing Source SelectAdvance Slave PLL TimingSlave CT Manual/Auto ModeSlave CT A/B SelectSlave CT A/B Read-back ReservedDefinitionSlave Bus Mode [1:0] (C_ [9:8]) (Read/Write) [1]00011011→ → → → CT Bus - Slave to CT_C8 & CT_FRAME (see Slave CT A/B Select) (Default)SCbus - Slave to SCLK & FR_COMPMVIP - Slave to C2 & FR_COMPLocal - Slave to L_CLK & L_FS (see Slave Local Timing Source Select)1.When local slave mode is selected, L_CLK frequency, polarity and output enable, and L_FS polarity, position and output enable must be configuredaccordingly.Slave Local Timing Source Select (C_ [10]) (Read/Write)01→ → L_CLK_0, L_FS_0 (Default)L_CLK_1, L_FS_1Advance Slave PLL Timing (C_ [11]) (Read/Write)The slave PLL timing may be advanced one 7.6 ns period to compensate for delay. Set to 0 for normal operation.01→ → Advance Slave PLL Timing Disabled (Default)Advance Slave PLL Timing EnabledSlave CT Manual/Auto Mode (C_ [12]) (Read/Write) [1]01→ → Slave CT Manual Mode (Default)Slave CT Auto Mode1.In auto mode, slave will only switch when an error exists on the current signal set and NOT on the other signal set.Slave CT A/B Select (C_ [13]) (Read/Write)Select signal set in manual mode then switch to auto.01→ → CT A Select (Default)CT B SelectSlave CT A/B Read-back (C_ [14]) (Read Only)01→ → CT A SelectedCT B SelectedOki Semiconductor17

Configuration Register Byte 2, AR = 0002hDR_001234567C1617181920212223Master CT EnableMaster CT A/B SelectReservedAdvance Master PLL TimingMaster Manual/Auto ModeMaster Primary/Secondary SelectMaster Primary/Secondary Read-backReservedDefinitionMaster CT Enable (C_ [16]) (Read/Write)Enables the Master PLL to drive the CT Bus.01→ → Master Disabled (Default)Master EnabledMaster CT A/B Select (C_ [17]) (Read/Write) [1]Selects the signal set driven by the Master PLL.01→ → CT_C8_A & CT_FRAME_A (Default)CT_C8_B & CT_FRAME_B1.When in Secondary Master mode, the signal set (A or B) NOT selected here is used as the reference.Advance Master PLL Timing (C_ [19]) (Read/Write)When operating as secondary master, the master PLL timing may be advanced one 7.6 ns clock period to compensate for delay.Set to 0 for normal operation.01→ → Advance Master PLL Timing Disabled (Default)Advance Master PLL Timing EnabledMaster Manual/Auto Mode (C_ [20]) (Read/Write) [1]01→ → Master Manual Mode (Default)Master Auto Mode1.Master Auto mode allows Secondary Master to become Primary if an error occurs on the reference signal set. To switch back to Secondary Masterit is necessary to go into manual mode.Master Primary/Secondary Select (C_ [21]) (Read/Write)01→ → Primary Master Select (Default)Secondary Master SelectMaster Primary/Secondary Read-back (C_ [22]) (Read Only)01→ → Primary Master SelectedSecondary Master Selected18Oki Semiconductor

Configuration Register Byte 3, AR = 0003hDR_0[1:0]234567C[25:24]262728293031SCbus SCLK Frequency [1:0]SCbus Master Enable - SCLK, SCLKX2 & FR_COMPReservedMVIP-90 Master Enable - C2, C4 & FR_COMPH-MVIP Master Enable - C2, C4, C16 & FR_COMPReservedReservedDefinitionSCbus SCLK Frequency [1:0] (C_ [25:24]) (Read/Write)00011011→ → → → 2.048 MHz (Default)4.096 MHz8.192 MHzReservedSCbus Master Enable (C_ [26]) (Read/Write)When enabled as Primary Master, this register enables the SCLK, SCLKX2 & FR_COMP signals to be driven.01→ → SCbus Master Disabled (Default)SCbus Master Enabled MVIP-90 Master Enable (C_ [28]) (Read/Write)When enabled as Primary Master, this register enables the C2, C4 & FR_COMP signals to be driven.01→ → MVIP-90 Master Disabled (Default)MVIP-90 Master Enabled H-MVIP Master Enable (C_ [29]) (Read/Write)When enabled as Primary Master, this register enables the C2, C4, C16 & FR_COMP signals to be driven.01→ → H-MVIP Master Disabled (Default)H-MVIP Master Enabled Oki Semiconductor19

Configuration Register Byte 4, AR = 0004hDR_0[2:0]3[5:4]67C[34:32]35[37:36]3839Master PLL Mode [2:0]ReservedMaster PLL Mode Read-back [1:0]Condition Master PLL ReferenceReservedDefinitionMaster PLL Mode [2:0] (C_ [34:32]) (Read/Write) [1]000001010011100101110111→ → → → → → → → Normal (Default)ReservedHoldoverFree RunReservedReservedAuto Normal to Holdover switch on Master PLL errorAuto Normal to Free Run switch on Master PLL error1.Master PLL error occurs when the Master PLL is out of lock with its reference signal. It is necessary to manually select \"Normal\" to go back tonormal operation after an auto switch has occurred.Master PLL Mode Read-back [1:0] (C_ [37:36]) (Read Only)00011011→ → → → NormalReservedHoldoverFree RunCondition Master PLL Reference (C_ [38]) (Read/Write)When enabled, conditions a change in references for MTIE compatibility.01→ → Condition Master PLL Reference Disabled (Default)Condition Master PLL Reference Enabled 20Oki Semiconductor

Configuration Register Byte 5, AR = 0005hDR_0[3:0]4[6:5]7C[43:40]44[46:45]47Master PLL Reference Select [3:0]ReservedMaster PLL Reference Frequency [1:0]ReservedDefinitionMaster PLL Reference Select [3:0] (C_ [43:40]) (Read/Write)0h1h2h3h4h5h6h7h8h9hahbhchdhehfh→ → → → → → → → → → → → → → → → None (Default)ReservedReservedReservedReservedReservedCT_NETREF_1CT_NETREF_2L_NETREF_0L_NETREF_1L_NETREF_2L_NETREF_3L_NETREF_4L_NETREF_5L_NETREF_6L_NETREF_7Master PLL Reference Frequency [1:0] (C_ [46:45]) (Read/Write)00011011→ → → → 8 kHz (Default)1.536 MHz1.544 MHz2.048 MHzOki Semiconductor21

Configuration Register Byte 6, AR = 0006hDR_0[3:0]4[6:5]7C[51:48]52[54:53]55CT_NETREF_1 Source Select [3:0]ReservedCT_NETREF_1 Divider [1:0]CT_NETREF_1 Output EnableDefinitionCT_NETREF_1 Source Select [3:0] (C_ [51:48]) (Read/Write)0h1h2h3h4h5h6h7h8h9hahbhchdhehfh→ → → → → → → → → → → → → → → → None (Default)ReservedReservedReservedReservedReservedReservedReservedL_NETREF_0L_NETREF_1L_NETREF_2L_NETREF_3L_NETREF_4L_NETREF_5L_NETREF_6L_NETREF_7CT_NETREF_1 Divider [1:0] (C_ [54:53]) (Read/Write)00011011→ → → → Divide source by 1 (Default)Divide source by 192Divide source by 193Divide source by 256CT_NETREF_1 Output Enable (C_ [55]) (Read/Write)01→ → CT_NETREF_1 Output Tri-stated (Default)CT_NETREF_1 Output Enabled22Oki Semiconductor

Configuration Register Byte 7, AR = 0007hDR_0[3:0]4[6:5]7C[59:56]60[62:61]63CT_NETREF_2 Source Select [3:0]ReservedCT_NETREF_2 Divider [1:0]CT_NETREF_2 Output EnableDefinitionCT_NETREF_2 Source Select [3:0] (C_ [59:56]) (Read/Write)0h1h2h3h4h5h6h7h8h9hahbhchdhehfh→ → → → → → → → → → → → → → → → None (Default)ReservedReservedReservedReservedReservedReservedReservedL_NETREF_0L_NETREF_1L_NETREF_2L_NETREF_3L_NETREF_4L_NETREF_5L_NETREF_6L_NETREF_7CT_NETREF_2 Divider [1:0] (C_ [62:61]) (Read/Write)00011011→ → → → Divide source by 1 (Default)Divide source by 192Divide source by 193Divide source by 256CT_NETREF_2 Output Enable (C_ [63]) (Read/Write)01→ → CT_NETREF_2 Output Tri-stated (Default)CT_NETREF_2 Output EnabledOki Semiconductor23

Configuration Register Byte 8, AR = 0008hDR_001234567C6465666768697071L_CLK_0, L_FS_0 Output EnableL_CLK_1, L_FS_1 Output EnableCT_D_ Output Enable ModeCT_D_DISABLE Output EnableCT_D_DISABLECT_D_DISABLE On InputCT_D_DISABLE On ErrorCT_D_DISABLE Read-backDefinitionL_CLK_0, L_FS_0 Output Enable (C_ [64]) (Read/Write)01→ → L_CLK_0, L_FS_0 Output Tri-stated (Default)L_CLK_0, L_FS_0 Output EnabledL_CLK_1, L_FS_1 Output Enable (C_ [65]) (Read/Write)01→ → L_CLK_1, L_FS_1 Output Tri-stated (Default)L_CLK_1, L_FS_1 Output EnabledCT_D_ Output Enable Mode (C_ [66]) (Read/Write)01→ → CT_D_[31:0] Output Tri-stated before bit cell boundary - Based on H.100/H.110 (Default)CT_D_[31:0] Output Tri-stated at bit cell boundaryCT_D_DISABLE Output Enable (C_ [67]) (Read/Write)01→ → CT_D_DISABLE pin Output Tri-stated (Default)CT_D_DISABLE pin Output EnabledCT_D_DISABLE (C_ [68]) (Read/Write)01→ → CT_D_ Outputs Enabled (Default)CT_D_ Outputs DisabledCT_D_DISABLE On Input (C_ [69]) (Read/Write)01→ → CT_D_DISABLE On Input Disabled (Default)CT_D_DISABLE On Input EnabledCT_D_DISABLE On Error (C_ [70]) (Read/Write)01→ → CT_D_DISABLE On Error Disabled (Default)CT_D_DISABLE On Error EnabledCT_D_DISABLE Read-back (C_ [71]) (Read Only)01→ → CT_D_ Outputs EnabledCT_D_ Outputs Disabled24Oki Semiconductor

Configuration Register Byte 9, AR = 0009hDR_0[1:0][3:2]45[7:6]C[73:72][75:74]7677[79:78]L_SI_[3:0], L_SO_[3:0] Stream Rate [1:0]L_CLK_0 Frequency [1:0]L_CLK_0 PolarityL_FS_0 PolarityL_FS_0 Position [1:0]DefinitionL_SI_[3:0], L_SO_[3:0] Stream Rate [1:0] (C_ [73:72]) (Read/Write)00011011→ → → → 2.048 Mb/s (L_SI_[3:0], L_SO_[3:0]) (Default) 4.096 Mb/s (L_SI_[1:0], L_SO_[1:0])8.192 Mb/s (L_SI_[0], L_SO_[0])ReservedL_CLK_0 Frequency [1:0] (C_ [75:74]) (Read/Write) [1]00011011→ → → → 2.048 MHz (Default)4.096 MHz8.192 MHz16.384 MHz1.Note: the L_CLK_0 frequency need not match the L_SI and L_SO stream frequencies, neither need it match the CT_C8 frequency when configuredas slave-to-CT.L_CLK_0 Polarity (C_ [76]) (Read/Write)01→ → L_CLK_0 Non-Inverted (Default) L_CLK_0 InvertedL_FS_0 Polarity (C_ [77]) (Read/Write)01→ → L_FS_0 Non-Inverted (Default)L_FS_0 InvertedL_FS_0 Position [1:0] (C_ [79:78]) (Read/Write)00011011→ → → → Early - L_FS_0 occurs during the last L_CLK_0 period of the frame (Default)Straddle - L_FS_0 straddles the frame boundaryLate - L_FS_0 occurs during the first L_CLK_0 period of the frameReserved Oki Semiconductor25

Configuration Register Byte 10, AR = 000ahDR_0[1:0][3:2]45[7:6]C[81:80][83:82]8485[87:86]L_SI_[7:4], L_SO_[7:4] Stream Rate [1:0]L_CLK_1 Frequency [1:0]L_CLK_1 PolarityL_FS_1 PolarityL_FS_1 Position [1:0]DefinitionL_SI_[7:4], L_SO_[7:4] Stream Rate [1:0] (C_ [81:80]) (Read/Write)00011011→ → → → 2.048 Mb/s (L_SI_[7:4], L_SO_[7:4]) (Default) 4.096 Mb/s (L_SI_[5:4], L_SO_[5:4])8.192 Mb/s (L_SI_[4], L_SO_[4])ReservedL_CLK_1 Frequency [1:0] (C_ [83:82]) (Read/Write) [1]00011011→ → → → 2.048 MHz (Default)4.096 MHz8.192 MHz16.384 MHz1.Note: the L_CLK_1 frequency need not match the L_SI and L_SO stream frequencies, neither need it match the CT_C8 frequency when configuredas slave-to-CT.L_CLK_1 Polarity (C_ [84]) (Read/Write)01→ → L_CLK_1 Non-Inverted (Default) L_CLK_1 InvertedL_FS_1 Polarity (C_ [85]) (Read/Write)01→ → L_FS_1 Non-Inverted (Default)L_FS_1 InvertedL_FS_1 Position [1:0] (C_ [87:86]) (Read/Write)00011011→ → → → Early - L_FS_1 occurs during the last L_CLK_1 period of the frame (Default)Straddle - L_FS_1 straddles the frame boundaryLate - L_FS_1 occurs during the first L_CLK_1 period of the frameReserved26Oki Semiconductor

Configuration Register Byte 11, AR = 000bhDR_0[1:0][3:2][5:4][7:6]C[89:88][91:90][93:92][95:94]CT_D_[3:0] Data Stream Rate [1:0]CT_D_[7:4] Data Stream Rate [1:0]CT_D_[11:8] Data Stream Rate [1:0]CT_D_[15:12] Data Stream Rate [1:0]DefinitionCT_D_[3:0] Data Stream Rate [1:0] (C_ [89:88]) (Read/Write)00011011→ → → → 2.048 Mb/s4.096 Mb/s8.192 Mb/s (Default)ReservedCT_D_[7:4] Data Stream Rate [1:0] (C_ [91:90]) (Read/Write)00011011→ → → → 2.048 Mb/s4.096 Mb/s8.192 Mb/s (Default)ReservedCT_D_[11:8] Data Stream Rate [1:0] (C_ [93:92]) (Read/Write)00011011→ → → → 2.048 Mb/s4.096 Mb/s8.192 Mb/s (Default)ReservedCT_D_[15:12] Data Stream Rate [1:0] (C_ [95:94]) (Read/Write)00011011→ → → → 2.048 Mb/s4.096 Mb/s8.192 Mb/s (Default)ReservedOki Semiconductor27

Configuration Register Byte 12, AR = 000chDR_001234567C96979899100101102103Direct Parallel Access EnableMicroprocessor Watchdog EnableAPLL Clock Watchdog EnableReservedMessage Channel Registered TXD EnableMessage Channel Output DisableReservedReservedDefinitionDirect Parallel Access Enable (C_ [96]) (Read/Write)01→ → Direct Parallel Access disabled (Default) Direct Parallel Access enabledMicroprocessor Watchdog Enable (C_ [97]) (Read/Write)When enabled, the ML53812-2 enters into reset after the Analog PLL clocks for 256mS (± 50%).Each time C_[97] is cleared (0) and then set (1), the microprocessor watchdog count is reset.01→ → Microprocessor Watchdog disabled (Default) Microprocessor Watchdog enabledAPLL Clock Watchdog Enable (C_ [98]) (Read/Write)When enabled, C_[98] will read back as being set (1) until the Analog PLL clocks for 125 µS (± 50%), then will read back as being cleared (0). Each time C_[98] is cleared (0) and then set (1), the clock watchdog count is reset.01→ → APLL Clock Watchdog disabled (Default) APLL Clock Watchdog enabledMessage Channel Registered TXD Enable (C_ [100]) (Read/Write)01→ → MC_TXD passed though to CT_MC (Default) MC_TXD registered to CT_MC on rising edge of MC_CLKMessage Channel Output Disable with Loop-back (C_ [101]) (Read/Write)When CT_MC output is disabled, the local message channel circuitry can be tested without disturbing the CT Bus.01→ → CT_MC Output enabled (Default) CT_MC Output Tri-stated, MC_TXD looped back to MC_RXD28Oki Semiconductor

Configuration Register Byte 13, AR = 000dhDR_001234567C104105106107108109110111INT PolarityINT MaskINT Output Driver ConfigurationINTReservedReservedReservedReservedDefinitionINT Polarity (C_ [104]) (Read/Write)01→ → INT Active Low (Default) INT Active HighINT Mask (C_ [105]) (Read/Write)01→ → INT Unmasked INT Masked (Default)INT Output Driver Configuration (C_ [106]) (Read/Write)01→ → Open Drain (Default) Push-PullINT (C_ [107]) (Read Only)This register is the logical or of all unmasked interrupt sources.01→ → All unmasked interrupts falseAny unmasked interrupt trueOki Semiconductor29

Configuration Register Byte 14, AR = 000eh [1]DR_001234567C112113114115116117118119CT Bus A Error Interrupt MaskCT Bus B Error Interrupt MaskSCbus Error Interrupt MaskMVIP Error Interrupt MaskMaster PLL Error Interrupt MaskFrame Boundary Interrupt MaskReservedReservedDefinition1.Masking an interrupt disables that interrupt from being OR’ed together with other interrupts to the INT pin. The state of the latches are accessiblewhile masked (polling mode).CT Bus A Error Interrupt Mask (C_ [112]) (Read/Write)01→ → CT Bus A Error Interrupt Unmasked CT Bus A Error Interrupt Masked (Default)CT Bus B Error Interrupt Mask (C_ [113]) (Read/Write)01→ → CT Bus B Error Interrupt Unmasked CT Bus B Error Interrupt Masked (Default)SCbus Error Interrupt Mask (C_ [114]) (Read/Write)01→ → SCbus Error Interrupt Unmasked SCbus Error Interrupt Masked (Default)MVIP Error Interrupt Mask (C_ [115]) (Read/Write)01→ → MVIP Error Interrupt Unmasked MVIP Error Interrupt Masked (Default)Master PLL Error Interrupt Mask (C_ [116]) (Read/Write)01→ → Master PLL Error Interrupt Unmasked Master PLL Error Interrupt Masked (Default)Frame Boundary Interrupt Mask (C_ [117]) (Read/Write)01→ → Frame Boundary Interrupt Unmasked Frame Boundary Interrupt Masked (Default)30Oki Semiconductor

Configuration Register Byte 15, AR = 000fhDR_001234567C120121122123124125126127CT Bus A Error Latch Clear CT Bus B Error Latch ClearSCbus Error Latch ClearMVIP Error Latch ClearMaster PLL Error Latch ClearFrame Boundary Latch ClearReservedReservedDefinitionCT Bus A Error Latch Clear (C_ [120]) (Read/Write)01→ → CT Bus A Error Latch EnabledCT Bus A Error Latch held clear (Default)CT Bus B Error Latch Clear (C_ [121]) (Read/Write)01→ → CT Bus B Error Latch EnabledCT Bus B Error Latch held clear (Default)SCbus Error Latch Clear (C_ [122]) (Read/Write)01→ → SCbus Error Latch EnabledSCbus Error Latch held clear (Default)MVIP Error Latch Clear (C_ [123]) (Read/Write)01→ → MVIP Error Latch EnabledMVIP Error Latch held clear (Default)Master PLL Error Latch Clear (C_ [124]) (Read/Write)01→ → Master PLL Error Latch EnabledMaster PLL Error Latch held clear (Default)Frame Boundary Latch Clear (C_ [125]) (Read/Write)01→ → Frame Boundary Latch EnabledFrame Boundary Latch held clear (Default)Oki Semiconductor31

Configuration Register Byte 16, AR = 0010hDR_001234567C128129130131132133134135CT Bus A Error LatchCT Bus B Error LatchSCbus Error LatchMVIP Error LatchMaster PLL Error LatchFrame Boundary LatchReservedReservedDefinitionCT Bus A Error Latch (C_ [128]) (Read Only)01→ → CT Bus A Error Latch FalseCT Bus A Error Latch TrueCT Bus B Error Latch (C_ [129]) (Read Only)01→ → CT Bus B Error Latch FalseCT Bus B Error Latch TrueSCbus Error Latch (C_ [130]) (Read Only)01→ → SCbus Error Latch FalseSCbus Error Latch TrueMVIP Error Latch (C_ [131]) (Read Only)01→ → MVIP Error Latch FalseMVIP Error Latch TrueMaster PLL Error Latch (C_ [132]) (Read Only)01→ → Master PLL Error Latch FalseMaster PLL Error Latch TrueFrame Boundary Latch (C_ [133]) (Read Only)01→ → Frame Boundary Latch FalseFrame Boundary Latch True32Oki Semiconductor

Configuration Register Byte 17, AR = 0011hDR_001234567C136137138139140141142143GPIO_0 InputGPIO_0 OutputGPIO_0 Output EnableGPIO_0 Output Driver ConfigurationGPIO _0 Latch PolarityGPIO _0 Interrupt MaskGPIO _0 Latch ClearGPIO _0 LatchDefinitionGPIO_0 Input (C_ [136]) (Read Only)01→ → GPIO_0 Input = 0GPIO_0 Input = 1GPIO_0 Output (C_ [137]) (Read/Write)01→ → GPIO_0 Output = 0 (Default)GPIO_0 Output = 1GPIO_0 Output Enable (C_ [138]) (Read/Write)01→ → GPIO_0 Output Tri-stated (Default)GPIO_0 Output EnabledGPIO_0 Output Driver Configuration (C_ [139]) (Read/Write)01→ → Open Drain (Default) Push-PullGPIO _0 Latch Polarity (C_ [140]) (Read/Write)01→ → GPIO _0 Latch set when GPIO_0 input = 0 (Default)GPIO _0 Latch set when GPIO_0 input = 1GPIO _0 Interrupt Mask (C_ [141]) (Read/Write)01→ → GPIO _0 Interrupt Unmasked GPIO _0 Interrupt Masked (Default)GPIO _0 Latch Clear (C_ [142]) (Read/Write)01→ → GPIO _0 Latch EnabledGPIO _0 Latch held clear (Default)GPIO _0 Latch (C_ [143]) (Read Only)01→ → GPIO _0 Latch FalseGPIO _0 Latch TrueOki Semiconductor33

Configuration Register Byte 18, AR = 0012hDR_001234567C144145146147148149150151GPIO_1 InputGPIO_1 OutputGPIO_1 Output EnableGPIO_1 Output Driver ConfigurationGPIO _1 Latch PolarityGPIO _1 Interrupt MaskGPIO _1 Latch ClearGPIO _1 LatchDefinitionGPIO_1 Input (C_ [144]) (Read Only)01→ → GPIO_1 Input = 0GPIO_1 Input = 1GPIO_1 Output (C_ [145]) (Read/Write)01→ → GPIO_1 Output = 0 (Default)GPIO_1 Output = 1GPIO_1 Output Enable (C_ [146]) (Read/Write)01→ → GPIO_1 Output Tri-stated (Default)GPIO_1 Output EnabledGPIO_1 Output Driver Configuration (C_ [147]) (Read/Write)01→ → Open Drain (Default) Push-PullGPIO _1 Latch Polarity (C_ [148]) (Read/Write)01→ → GPIO _1 Latch set when GPIO_1 input = 0 (Default)GPIO _1 Latch set when GPIO_1 input = 1GPIO _1 Interrupt Mask (C_ [149]) (Read/Write)01→ → GPIO _1 Interrupt Unmasked GPIO _1 Interrupt Masked (Default)GPIO _1 Latch Clear (C_ [150]) (Read/Write)01→ → GPIO _1 Latch EnabledGPIO _1 Latch held clear (Default)GPIO _1 Latch (C_ [151]) (Read Only)01→ → GPIO _1 Latch FalseGPIO _1 Latch True34Oki Semiconductor

Configuration Register Byte 19, AR = 0013hDR_001234567C152153154155156157158159GPIO_2 InputGPIO_2 OutputGPIO_2 Output EnableGPIO_2 Output Driver ConfigurationGPIO _2 Latch PolarityGPIO _2 Interrupt MaskGPIO _2 Latch ClearGPIO _2 LatchDefinitionGPIO_2 Input (C_ [152]) (Read Only)01→ → GPIO_2 Input = 0GPIO_2 Input = 1GPIO_2 Output (C_ [153]) (Read/Write)01→ → GPIO_2 Output = 0 (Default)GPIO_2 Output = 1GPIO_2 Output Enable (C_ [154]) (Read/Write)01→ → GPIO_2 Output Tri-stated (Default)GPIO_2 Output EnabledGPIO_2 Output Driver Configuration (C_ [155]) (Read/Write)01→ → Open Drain (Default) Push-PullGPIO _2 Latch Polarity (C_ [156]) (Read/Write)01→ → GPIO _2 Latch set when GPIO_2 input = 0 (Default)GPIO _2 Latch set when GPIO_2 input = 1GPIO _2 Interrupt Mask (C_ [157]) (Read/Write)01→ → GPIO _2 Interrupt Unmasked GPIO _2 Interrupt Masked (Default)GPIO _2 Latch Clear (C_ [158]) (Read/Write)01→ → GPIO _2 Latch EnabledGPIO _2 Latch held clear (Default)GPIO _2 Latch (C_ [159]) (Read Only)01→ → GPIO _2 Latch FalseGPIO _2 Latch TrueOki Semiconductor35

Configuration Register Byte 20, AR = 0014hDR_001234567C160161162163164165166167GPIO_3 InputGPIO_3 OutputGPIO_3 Output EnableGPIO_3 Output Driver ConfigurationGPIO _3 Latch PolarityGPIO _3 Interrupt MaskGPIO _3 Latch ClearGPIO _3 LatchDefinitionGPIO_3 Input (C_ [160]) (Read Only)01→ → GPIO_3 Input = 0GPIO_3 Input = 1GPIO_3 Output (C_ [161]) (Read/Write)01→ → GPIO_3 Output = 0 (Default)GPIO_3 Output = 1GPIO_3 Output Enable (C_ [162]) (Read/Write)01→ → GPIO_3 Output Tri-stated (Default)GPIO_3 Output EnabledGPIO_3 Output Driver Configuration (C_ [163]) (Read/Write)01→ → Open Drain (Default) Push-PullGPIO _3 Latch Polarity (C_ [164]) (Read/Write)01→ → GPIO _3 Latch set when GPIO_3 input = 0 (Default)GPIO _3 Latch set when GPIO_3 input = 1GPIO _3 Interrupt Mask (C_ [165]) (Read/Write)01→ → GPIO _3 Interrupt Unmasked GPIO _3 Interrupt Masked (Default)GPIO _3 Latch Clear (C_ [166]) (Read/Write)01→ → GPIO _3 Latch EnabledGPIO _3 Latch held clear (Default)GPIO _3 Latch (C_ [167]) (Read Only)01→ → GPIO _3 Latch FalseGPIO _3 Latch True36Oki Semiconductor

6.5 Device ID Registers (Read Only)Device ID byte 3, AR = 00ffhDR_0[7:4][3:0]Version [3:0]Part Number [15:12]DefinitionDevice ID byte 2, AR = 00fehDR_0[7:0]Part Number [11:4]DefinitionDevice ID byte 1, AR = 00fdhDR_0[7:4][3:0]Part Number [3:0]Manufacturer ID [10:7]DefinitionDevice ID byte 0, AR = 00fchDR_0[7:1]0Manufacturer ID [6:0]0 = Device does not support Boundary Scan 1 = Device supports Boundary ScanML53812-2 Device ID byte [3:0] = 20 8c 00 00hDefinitionOki Semiconductor37

6.6 Stream Switch Routing Registers, AR = 1007h:1000h (Ch. 7:0)Note: To ensure compatibility with possible future versions of this device, write “0” to all \"Reserved\" bits in the routing registers. All \"Reserved\" routing registers read-back \"0\".DR_0[4:0][7:5]Input Data Stream [4:0]Reserved (write zero)DefinitionInput Data Stream [4:0] (Read/Write)00h01h02h••1eh1fhDR_1[4:0][6:5]7Output Data Stream [4:0]Reserved (write zero)Output Enable→ → → → → CT_D_[0] (Default)CT_D_[1]CT_D_[2] • •CT_D_[30]CT_D_[31]DefinitionOutput Data Stream [4:0] (Read/Write)00h01h02h••1eh1fh→ → → → → CT_D_[0] (Default)CT_D_[1]CT_D_[2] • •CT_D_[30]CT_D_[31]Output Enable (Read/Write)01→ → Output Disabled (Default)Output EnabledDR_2[1:0][7:2]Partition [1:0]Reserved (write zero)DefinitionPartition [1:0] (Read/Write)Selects which time-slots are used when rate conversion is taking place. See the following table for adescription of the partition function. 38Oki Semiconductor

6.7 Stream Switch Connection MappingInput DataStream Rate2 Mb/sOutput Data Stream Rate2 Mb/s4 Mb/sPartition0018 Mb/s01234 Mb/s2 Mb/s014 Mb/s8 Mb/s0018 Mb/s2 Mb/s01234 Mb/s018 Mb/s0Timeslot Connection0 to 1, 1 to 2, 2 to 3, … , 31 to 00 to 2, 1 to 4, 2 to 6, … , 31 to 00 to 3, 1 to 5, 2 to 7, … , 31 to 10 to 4, 1 to 8, 2 to 12, … , 31 to 00 to 5, 1 to 9, 2 to 13, … , 31 to 10 to 6, 1 to 10, 2 to 14, … , 31 to 20 to 7, 1 to 11, 2 to 15, … , 31 to 30 to 1, 2 to 2, 4 to 3, … , 62 to 01 to 1, 3 to 2, 5 to 3, … , 63 to 00 to 1, 1 to 2, 2 to 3, … , 63 to 00 to 2, 1 to 4, 2 to 6, … , 63 to 00 to 3, 1 to 5, 2 to 7, … , 63 to 10 to 1, 4 to 2, 8 to 3, … , 124 to 01 to 1, 5 to 2, 9 to 3, … , 125 to 02 to 1, 6 to 2, 10 to 3, … , 126 to 03 to 1, 7 to 2, 11 to 3, … , 127 to 00 to 1, 2 to 2, 4 to 3, … , 126 to 01 to 1, 3 to 2, 5 to 3, … , 127 to 00 to 1, 1 to 2, 2 to 3, … , 127 to 0Frame BoundaryCT_D time-slots @ 8mb/sCT_D time-slots @ 4mb/sCT_D time-slots @ 2mb/s123123301246231125126631270001213421Figure 5. CT Bus Data Stream SwitchingThe Stream Switch provides a data stream-to-data stream connection capability. Switching between anyof the 32 CT Bus data streams operating at 2, 4, or 8 Mb/s is supported. Eight stream switch channels areprovided. Individual time-slots are not tri-state controlled. Buffering is done on single timeslots ratherthan entire frames. This trade-off complicates the connection matrix, but without this compromise itwould not be practical to implement the Stream Switch.Depending upon the data stream rates, the stream switch provides a minimum of 256 and a maximum of1024 uni-directional timeslot connections. Stream switches in other ML53812-2 devices in a system maybe used simultaneously to increase switching capability. The output of the stream switch is multiplexedwith the output of the transmit switch, with the transmit switch having priority.Oki Semiconductor39

The main application of the Stream Switch is to provide an inter-rate exchange highway allowing legacyBus devices operating at different rates to exchange data.A typical configuration of the Stream Switch using 2 switch channels and 3 streams to provide 32 fullduplex connections between SCbus (operating at 4 MHz) and MVIP is outlined below.Example:Stream switch channel 0 is configured with CT_D_0 as the input data stream and the even time-slots(partition = 0) of CT_D_8 as the output data stream.Stream switch channel 1 is configured with the odd timeslots (partition = 1) of CT_D_8 as the input datastream and CT_D_1 as the output data stream.CT_D _0 (MVIP)CT_D _1 (MVIP)CT_D _8 (SCbus)31006301211342Figure 6. Data Stream Switching Example40Oki Semiconductor

6.8 Transmit Switch Routing Registers, AR = 20ffh:2000h (Ch. 255:0)Note: To ensure compatibility with subsequent versions of this device, write “0” to all \"Reserved\" bits in the routing registers. All \"Reserved\" routing registers read-back \"0\".DR_0[6:0]7Output Time-slot Reserved (write zero)DefinitionOutput Time-slot [6:0] (Read/Write)Selects the CT_D time-slot for transmit channel routing.00h01h02h••7eh7fh→ → → → → Time-slot 0 (Default)Time-slot 1Time-slot 2 • •Time-slot 126Time-slot 127Note: Internally all time-slots run at 8Mb/s. To transmit on CT_D data streams running at a slower rate, use the following conversion:If CT_D data stream is operating at 4Mb/s, transmit switch output time-slot = CT_D time-slot X 2.If CT_D data stream is operating at 2Mb/s, transmit switch output time-slot = CT_D time-slot X 4.DR_1[4:0][6:5]7Output Data StreamReserved (write zero)Output EnableDefinitionOutput Data Stream [4:0] (Read/Write)Selects the CT_D Data stream for transmit channel routing.00h01h02h••1eh1fh→ → → → → CT_D_[0] (Default)CT_D_[1]CT_D_[2] • •CT_D_[30]CT_D_[31]Output Enable (Read/Write)Controls the Output Enable for the selected CT Bus data stream and time-slot.01→ → Output Disabled (Default)Output EnabledOki Semiconductor41

DR_2012[7:3]DelayCT Bus ConnectSourceReserved (write zero)DefinitionDelay (Read/Write)Selects the switching delay mode. When set to Constant, data is switched on frame boundaries resulting in a constant 1 frame delay and allowing \"bundling\". When set to Minimum, data is switched on 2Mb/s timeslot boundaries reducing the delay through the switch for certain combinations of input to output time-slots.01→ → Constant (Default)MinimumNote: Do not use Minimum delay mode on channels using parallel data source.CT Bus Connect Enable (Read/Write)Enables the switch to be used for CT Bus to CT Bus connection without externally connecting L_SO to L_SI. When enabled, the L_SI input is replaced by the corresponding L_SO output. CT Bus connect allows inter-operability switching to be provided by any unused transmit and receive switch pair.01→ → CT Bus Connect Disabled (Default)CT Bus Connect EnabledNote: The receive switch output enable register does not have to be set to make this connection.Source (Read/Write)Selects the transmit channel data source. When set to 0, Serial TDM data from L_SI or L_SO (see CT Bus Connect Enable) is selected. When set to 1, the corresponding parallel access register is selected as the source of the transmit channel data. 01→ → Serial TDM data (Default)Parallel microprocessor dataNote: The Serial TDM data and the parallel access register share common registers within the transmit switch. Therefore it is necessary to write to the parallel access register after the source is changed to parallel microprocessor data.42Oki Semiconductor

6.9 Receive Switch Routing Registers, AR = 30ffh:3000h (Ch. 255:0)Note: To ensure compatibility with subsequent versions of this device, write “0” to all \"Reserved\" bits in the routing registers. All \"Reserved\" routing registers read-back \"0\".DR_0[6:0]7Input Time-slot Reserved (write zero)DefinitionInput Time-slot [6:0] (Read/Write)Selects the CT_D time-slot for receive channel routing.00h01h02h••7eh7fh→ → → → → Time-slot 0 (Default)Time-slot 1Time-slot 2 • •Time-slot 126Time-slot 127Note: Internally all time-slots run at 8Mb/s. To receive from CT_D streams running at a slower rate, use the following conversion:If CT_D stream is operating at 4Mb/s, receive switch input time-slot register = CT_D time-slot X 2 + 1.If CT_D stream is operating at 2Mb/s, receive switch input time-slot register = CT_D time-slot X 4 + 3.DR_1[4:0][6:5]7Input Data StreamReserved (write zero)Output EnableDefinitionInput Data Stream [4:0] (Read/Write)Selects the CT_D data stream for receive channel routing.00h01h02h••1eh1fh→ → → → → CT_D_[0] (Default)CT_D_[1]CT_D_[2] • •CT_D_[30]CT_D_[31]Output Enable (Read/Write)Controls the Output Enable for the channel’s local stream.01→ → Output Disabled (Default)Output EnabledOki Semiconductor43

DR_2012[7:3]DelayLocal ConnectSourceReserved (write zero)DefinitionDelay (Read/Write)Selects the switching delay mode. When set to Constant, data is switched on frame boundaries resulting in a constant 1 frame delay and allowing \"bundling\". When set to Minimum, data is switched on 2Mb/s timeslot boundaries reducing the delay through the switch for certain combinations of input to output time-slots.01→ → Constant (Default)MinimumNote: Do not use Minimum delay mode on channels using parallel data source.Local Connect Enable (Read/Write)Enables the receive switch to be used for local connection. When enabled, a transmit channel is connected to a receive channel without using the CT Bus.01→ → Local Connect Disabled (Default)Local Connect EnabledNote: When Local Connect is Enabled, the Receive Switch routing registers DR_0 and DR_1 are redefined as the 8 bits of the transmit channel number instead of the CT_D time-slot and stream as shown below:DR_0_[6:0] DR_1_[7] DR_1_[0]→ → → Transmit channel bits [6:0]Output EnableTransmit Channel bit [7]Source (Read/Write)Selects the receive channel data source. When set to 0, Serial TDM data from the CT Bus data stream or transmit channel (see Local Connect Enable) is selected. When set to 1, the channels parallel access register is selected as the source of the receive channel data. 01→ → Serial TDM data (Default)Parallel microprocessor dataNote: The Serial TDM data and the parallel access register share common registers within the receive switch. Therefore it is necessary to write to the parallel access register after the source is changed to parallel microprocessor data.44Oki Semiconductor

6.10 Indirect Transmit Switch Parallel Access Registers, AR = 40ffh:4000h (Ch. 255:0)DR_0[7:0]TDM Data [1:8] DefinitionTDM Data [1:8] (Read/Write)Writing to this register provides the transmit data when the transmit switch channel is configured to use parallel microprocessor data as its source (to CT_D). This register and the serial input buffer share common hardware, therefore this register must be written after the transmit switch channel source is changed from serial TDM data to parallel microprocessor data.The transmit switch channel output buffer data obtained by reading the TDM data register. When the transmit switch channel is configured to use serial TDM data as its source, the data from the local SI channel can be monitored. When the transmit switch channel is configured to use parallel microprocessor data as its source, the data written into this register can be monitored. Note: When converted from parallel to serial, TDM Data Bit 1 is transmitted first.6.11 Indirect Receive Switch Parallel Access Registers, AR = 50ffh:5000h (Ch. 255:0)DR_0[7:0]TDM Data [1:8] DefinitionTDM Data [1:8] (Read/Write)Writing to this register provides the receive data when the receive switch channel is configured to use parallel microprocessor data as its source (to L_SO). This register and the serial input buffer share common hardware, so this register must be written after the receive switch channel source is changed from serial TDM data to parallel microprocessor data.The receive switch channel output buffer data is obtained by reading the TDM Data register. When the receive switch channel is configured to use serial TDM data as its source, the data from the CT_D stream and timeslot selected in the receive switch routing registers can be monitored. When the receive switch channel is configured to use parallel microprocessor data as its source, the data written into this register can be monitored.Note: When converted from parallel to serial, TDM Data Bit 1 is transmitted first.Oki Semiconductor45

7.0 ELECTRICAL SPECIFICATIONS7.1 Absolute Maximum RatingsParameterStorage TemperaturePower Supply VoltageInput VoltageTSVPSVISymbolTest ConditionsMin-65-0.3-0.3Max1504.66Unit°CVV7.2 Recommended Operating ConditionsParameterAmbient TemperatureSupply VoltageTAVDDSymbolTest ConditionsMin-403.0Max853.6Unit°CV7.3 DC Electrical CharacteristicsParameterCore Supply CurrentI/O Supply CurrentAnalog PLL Supply CurrentInput High Voltage Input Low Voltage Schmitt Input High Voltage Schmitt Input Low Voltage Schmitt Input Hysteresis Voltage Output High Voltage - PCIOutput Low Voltage - PCIOutput High Voltage – 24mAOutput Low Voltage – 24mAOutput High Voltage – 8mAOutput Low Voltage – 8mAOutput High Voltage – 6mAOutput Low Voltage – 6mA50 k Pull-up CurrentI/O Leakage CurrentSymbolIDDCIDDOIDDAVIHVILVt+Vt-VHYSVOH-PCIVOL-PCIVOH-24mAVOL-24mAVOH-8mAVOL-8mAVOH-6mAVOL-6mAIPILI/OIOH = -2 mAIOL = 6 mAIOH = -24 mAIOL = 24 mAIOH = -8 mAIOL = 8 mAIOH = -6 mAIOL = 6 mAVPAD = 0 VVI/O = VDD or VSS-152.40.4-170±102.40.42.40.4Test ConditionsVDDC = 3.6VVDDO = 3.6VVDDA = 3.6V2.0-0.52.05-0.5±0.42.40.55MinMax125140105.50.85.50.7UnitmAmAmAVVVVVVVVVVVVVµAµANOTES:1. PCI Drivers meet the AC Specifications for the PCI 5V signaling environment.2. Pin Capacitance: Input pins = 6 pF, Output pins = 9 pF, Bi-directional pins = 10 pF.46Oki Semiconductor

7.4 AC Electrical CharacteristicsNote: Signals ending in “_N” are active low.Microprocessor Interface Timing - Intel Bus Mode, Non-multiplexed Address [1] [2] [3]ParameterCS_N setup to WR_N ↑WR_N pulse widthA_[9:0] setup to WR_N ↓ (C_96=1)A_[2:0] setup to WR_N ↑(C_96=0)A_[9:0] hold from WR_N ↑D_[7:0] setup to WR_N ↑D_[7:0] hold from WR_N ↑D_[7:0] float to valid delay from CS_N RD_N, and A_[9:0]D_[7:0] valid to float delay from CS_N or RD_N1.Timing measured with 100 pF load on D_[7:0].2.Write cycle may be controlled by CS_N or WR_N.3.ALE=1.t1t2t3t4t5t6t7t8t9SymbolMin40405405405005010TypMaxUnitnsnsnsnsnsnsnsnsnst1CS_NRD_Nt2WR_Nt3t4A_[9:0]t5t6D_[7:0]t7t8t9Figure 7. Microprocessor Interface Timing - Intel Bus Mode, Non-multiplexed AddressOki Semiconductor47

Microprocessor Interface Timing - Motorola Bus Mode, Non-multiplexed Address [1] [2] [3]ParameterCS_N setup to STRB_N ↑STRB_N pulse widthR/W_N setup to STRB_N ↓R/W_N hold from STRB_N ↑A_[9:0] setup to STRB_N ↓ (C_96=1)A_[2:0] setup to STRB_N ↑ (C_96=0)A_[9:0] hold from STRB_N ↑D_[7:0] setup to STRB_N ↑D_[7:0] hold from STRB_N ↑D_[7:0] float to valid delay from CS_N, STRB_N, and A_[9:0]D_[7:0] valid to float delay from CS_N or STRB_N1.Timing measured with 100 pF load on D_[7:0].2.Write cycle may be controlled by CS_N or STRB_N.3.AS=1.t1t2t3t4t5t6t7t8t9t10t11SymbolMin4040555405405005010TypMaxUnitnsnsnsnsnsnsnsnsnsnsnst1CS_Nt2STRB_Nt3R/W_Nt5t6A_[9:0]t7t4t3t4t8D_[7:0]t9t10t11Figure 8. Microprocessor Interface Timing - Motorola Bus Mode, Non-multiplexed Address48Oki Semiconductor

Microprocessor Interface Timing - Multiplexed AddressParameterALE (AS) pulse widthA_[9:0] setup to ALE (AS) ↓A_[9:0] hold from ALE (AS) ↓t1t2t3SymbolMin2055TypMaxUnitnsnsnst1ALE (AS)t2t3A_[9:0]Figure 9. Microprocessor Interface Timing - Multiplexed AddressReset TimingParameterRESET pulse widtht1SymbolMin50TypMaxUnitnst1RESETFigure 10. Reset TimingOki Semiconductor49

Local Clock and Frame Synchronization Timing [1] [2]ParameterL_CLK period (2.048 MHz)L_CLK period (4.096 MHz)L_CLK period (8.192 MHz)L_CLK period (16.384 MHz)L_FS delay from L_CLK _ (Early position)L_FS delay from L_CLK _ (Straddle position)L_FS delay from L_CLK _ (Late position)Symbolt1at1bt1ct1dt2t3t4-10-10-10MinTyp48824412261+10+10+10MaxUnitnsnsnsnsnsnsns1.Timing measured with 100 pF load on all Local bus outputs.2.L_CLK and L_FS shown with positive polarity, timing is equivalent when signals are inverted.Local Clock to CT Bus Clock Skew [1]ParameterWith C_11 (Advance Slave DPLL Timing) set to 0 (default)With C_11 (Advance Slave DPLL Timing) set to 1Symbolt5t5MinTypMax+22.5 / -0+15 / -7.5UnitNsNs1.When reference L_CLK is more stable, there is no reduction in the amplitude of the skew, but a reduction in the number of occurrences. The furtheraway from the center frequency, the more frequently the skew occurs. The skew amplitude will jump in steps, but the range will remain the same.Test conditions were 65.536 MHz (C_[7:4]= 0) and 2.048 MHz (C_[7:4] = 6). Local Serial Stream Timing [1]ParameterL_SO float to valid delay from Bit Cell BoundaryL_SO valid to valid delay from Bit Cell BoundaryL_SO valid to float delay from Bit Cell Boundary2,048Mb/s Sample Point from Bit Cell Boundary4,096Mb/s Sample Point from Bit Cell Boundary8.192Mb/s Sample Point from Bit Cell BoundaryL_SI Setup to Sample PointL_SI Hold to Sample PointSymbolt6t7t8t9at9bt9ct10t111010Min-10-10-10+335.5+213.5+91.5TypMax+10+10+10Unitnsnsnsnsnsnsnsns1.The Bit Cell Boundary is defined by the relative edge of L_CLK (Figure 11 assumes that L_CLK and L_FS polarities are both non-inverted (C_[76] = 0; C_[77] = 0; C_[84] = 0; C_[85] = 0))50Oki Semiconductor

Frame Boundary (Bit Cell Boundary)t5CT_C8_A/BBit Cell Boundaryt1L_CLKBit Cell BoundaryBit Cell Boundaryt2L_FSt2t3L_FSt4L_FSt3t4t6L_SO_[7:0]t9t10L_SI_[7:0]t11t7t8Figure 11. Local Clock and Frame Synchronization TimingOki Semiconductor51

H.100/H.110 Clock Alignment(Extract from H.100/H.110 Specifications, Rev. 1.0)CT_FRAME_(A/B)_NCT_C8_(A/B)FR_COMP_NC16 _NC2C4 _NSCLK (2.048 MHz)SCLK x2* (2 x 2.048MHz)SCLK (4.096MHz)SCLK x2* (2 x 4.096MHz)SCLK (8.192MHz)SCLK x2* (2 x 8.192MHz)Note: C16_N, C2, and C4_N not defined in H.110.Figure 12. H.100/H.110 Clock Alignment52Oki Semiconductor

H.100/H.110 Frame Structure(Extract from H.100/H.110 Specifications, Rev. 1.0)125 µSCT_FRAME_(A/B)_NCT_C8_(A/B)CT_Dx812345678123456781Time Slot0127Figure 13. H.100/H.110 Frame StructureH.100/H.110 Detailed Data Bus Timing(Extract from H.100/H.110 Specifications, Rev. 1.0)1 Bit CellTfsCT_FRAME_(A/B)_NTfpTc8hCT_C8_(A/B)Tc8pTdozData OutTs 127 Bit 8TzdoTs 0 Bit 1TdivTdvData InTsamp1.4VTdod2.4V0.4VTc8I2.0V0.6VTfh2.0V0.6VFigure 14. H.100/H.110 Detailed Data Bus TimingOki Semiconductor53

7.5 H.100/H.110 Bus Timing Speciﬁcation(Extract from H.100/H.110 Specifications, Rev. 1.0)ParameterClock edge rate (All Clocks)CT_C8_(A/B) and CT_FRAME_(A/B)_N edge rateCT_NETREF edge rateClock CT_C8_(A/B) PeriodClock CT_C8_(A/B) High TimeH.100H.110Clock CT_C8_(A/B) Low TimeH.100H.110Data Sample PointData Output to HiZ TimeH.100H.110Data HiZ to Output TimeH.100H.110Data Output Delay TimeH.100H.110Data Valid TimeH.100H.110Data Invalid TimeH.100H.110CT_FRAME_(A/B)_N WidthCT_FRAME_(A/B)_N Setup TimeCT_FRAME_(A/B)_N Hold TimePhase Correction1.2.3.4.5.6.7.8.9.10.11.12.13.14.15.16.TfpTfsTfhΦTdivTdvTdodTzdoTsampTdoz-20-100000001021029045450122Tc8lH.100H.110H.110Tc8pTc8h122.066-Φ49-Φ63-Φ49-Φ63-Φ9000221122116983112112180909010SymbolMin0.250.25TypMax220.3122.074+Φ73+Φ69+Φ73+Φ69+ΦUnitV/nsV/nsV/nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns [17] [15] [16] [1] [1]Notes [2] [3] [4] [4] [5] [4] [4] [5] [6] [7] [8] [9] [8] [9] [10] [7] [8] [9] [8] [9] [10] [7] [8] [8] [10] [7] [11] [12] [11] [13] [14] The rise and fall times are determined by the edge rate in V/nS. A maximum edge rate is the fastest rate at which a clock transitions. 10% - 90%. Test Load = 150 pF.Tc8p Min and Max are under free-run conditions assuming ±32 ppm clock accuracy.Non-cumulative, Tc8p requirements still need to be met.Duty Cycle measured at transmitter under no load conditions.For reference onlyTest Load - 200 pFMeasured at the transmitter.Tdoz and Tzdo apply at every time-slot boundary.Test Load - 12 pFMeasured at the receiver.Reference only: Tdv = Max. clock cable delay + Max. data cable delay + Max. data HiZ to output time = 12nS + 35nS + 22 nS = 69nS. Max. clockcable delay and max. data cable delay are worst case numbers based on electrical simulation.Reference only: Tdv = Max. clock backplane delay + Max. data backplane delay + Max. data HiZ to output time = 26nS + 46nS + 11nS = 83nS. Max.clock delay and max. data delay are worst case numbers based on electrical simulation.Based on worst case electrical simulation.This range accounts for Φ (Phase Correction).Tcell = Max. clock backplane delay + Max. data backplane delay + Max. Tzdo + (Min. Tdiv - Max. Tdv) + Max Tdoz + F = 26nS + 46nS + 11nS +(102nS - 83nS) + 10nS + 10nS = 122nS. Max. clock delay and max. data delay are worst case numbers based on electrical simulation.54Oki Semiconductor

17.Φ (Phase Correction) results from PLL timing corrections.H.100. Measuring conditions:Data linesVth (threshold voltage) = 1.4VVhi (test high voltage) = 2.4VVlo (test low voltage) = 0.4VInput signal edge rate = 1 V/nSClock and Frame linesVt+ (test high voltage) = 2.0VVt- (test low) = 0.6VInput signal edge rate = 1 V/nSH.110. Measuring conditions:Data linesVhi (test high voltage) = 2.0VVlo (test low voltage) = 0.8VInput signal edge rate = 1 V/nSClock and Frame linesVt+ (test high voltage) = 2.0VVt- (test low voltage) = 0.6VInput signal edge rate = 1 V/nSOki Semiconductor55

7.6 Clock Skew Requirements(Extract from H.100/H.110 Specifications, Rev. 1.0)Parameter(H.100) Max Skew between CT_C8 \"A\" and \"B\"(H.110) Max Skew between CT_C8 \"A\" and \"B\"SymbolTskc8Tskc8MinTypMax±10 ±Φ±10 ±Φ±5±5UnitnsnsnsnsNotes [1] [2] [3] [4] [2] [3] [4] [5] [1](H.100) Max Skew between CT_C8_A and any Tskcompcompatibility clock (H.110) Max Skew between CT_C8_A and any Tskcompcompatibility clock [5]1.Test Load – 200 pF.2.Assumes \"A\" and \"B\" masters in adjacent slots.3.When static skew is 10nS and, in the same clock cycle, each clock performs a 10nS phase correction in opposite directions, a maximum skew of30nS will occur during that clock cycle.4.Meeting the skew requirements in Table 2 and the requirements of Section 2.3 (in the H.100/H.110 Specifications, Rev. 1.0) could require thePLL’s generating CT_C8 to have different time constants when acting as primary and secondary clock masters.5.Test Load - \"A\" load = \"B\" load. CT_C8_AVt+CT_C8_AVt+Tskc8CT_C8_BVt+Inter-operability ClocksVt+Vt-TskcompTskcompFigure 15. Clock Skew Requirements56Oki Semiconductor

8.0 ML53812-2 PACKAGE SPECIFICATIONS8.1 LQFP176 Package Outlines and Dimensions132891.25 TYP1338826.0 ± 0.2 sq.24.0 ± 0.1 sq.1.0 ± 0.2176450 ~ 10°1.7 MAX.1.4 ± 0.050 ~ 0.20.250.5 TYP0.6 ± 0.151.25 TYP10.5Index MarkMirror Finish0.22 ± 0.05440.10M0.17 ± 0.050.10Seating PlaneAll measurements are in millimeters or degreesOki Semiconductor57

8.2 LQFP176 Mounting Pad Reference Measurements0.50.2524.41.024.4LQFP176-P-2424-0.50-BKAll measurements are in millimeters58Oki Semiconductor

The information contained herein can change without notice owing to product and/or technical improvements.Please make sure before using the product that the information you are referring to is up-to-date.The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard actionand performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected inthe actual circuit and assembly designs.Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect,improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limitedto, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range.Neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection withthe use of product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of athird party's right which may result from the use thereof.When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges,including but not limited to operating voltage, power dissipation, and operating temperature.The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,officeautomation, communication equipment, measurement equipment, consumer electronics, etc.).These products are not authorized foruse in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or applicationwhere the failure of such system or application may result in the loss or damage of property or death or injury to humans. Suchapplications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, includinglife support and maintenance.Certain parts in this document may need governmental approval before they can be exported to certain countries. The purchaserassumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at theirown expense, for export to another country.Copyright 2000 Oki Semiconductor; Copyright 2000 Dialogic Corporation.This document may not, in whole or in part, be reproduced, stored in a retrieval system, translated, or transmitted in any form or by anymeans, electronic or mechanical, without the express written consent of Dialogic Corporation or Oki Semiconductor.This document contains preliminary information that is subject to change without notice. While every effort has been made to ensurethe accuracy of this document, due to ongoing improvements and revisions neither Dialogic nor Oki Semiconductor can guarantee theaccuracy of printed material after the date of publication, nor can they accept responsibility for errors or omissions. Dialogic and OkiSemiconductor reserve the right to make changes to the product(s) described, or information contained herein, as needed.Neither Dialogic Corporation nor Oki Semiconductor guarantees the suitability of the product(s) described for any particularimplementation. Nor does either company accept responsibility for any loss or damage of whatever nature resulting from the use of, orreliance upon, the information contained herein.Dialogic is a registered trademark, and CT612, SCSA, SCxbus, and the Signal Computing System Architecture are trademarks ofDialogic Corporation. CT Bus is a trademark of the Enterprise Computer Telephony Forum (ECTF). CompactPCI is a registeredtrademark of the PCI Industrial Computers Manufacturers Group (PICMG). MVIP and MVIP-90 are trademarks of NaturalMicroSystems. All other names, products, and services are the trademarks or registered trademarks of their respective organizations.Oki Semiconductor reserves the right to make changes in specifications at anytime and without notice. This information furnished byOki Semiconductor in this publication is believed to be accurate and reliable. However, no responsibility is assumed by OkiSemiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. No license isgranted under any patents or patent rights of Oki.Oki Semiconductor

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