Vertical integrated circuits

专利名称：Vertical integrated circuits发明人：Sadeg M Faris申请号：US11020753申请日：20041223公开号：US07145219B2公开日：20061205

专利附图：

摘要：A method for fabricating a vertical integrated circuit is disclosed. Integratedcircuits are fabricated on a substrate with layers of predetermined weak and strong bondregions where deconstructed layers of integrated circuits are fabricated at or on theweak bond regions. The layers are then peeled and subsequently bonded to produce a

vertical integrated circuit. An arbitrary number of layers can be bonded and stacked in toa separate vertical integrated circuit. Also disclosed are methods of creating edgeinterconnects and vias through the substrate to form interconnections between layersand devices thereon.

申请人：Sadeg M Faris

地址：Pleasantville NY US

国籍：US

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