ADS单通道触摸芯片TS01S应用参考设计方案 (1)

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下面奥伟斯将给大家详细介绍TS01S 相关信息：TS01S (1-CH Differential Sensitivity Calibration Capacitive Touch Sensor)

SPECIFICATION VER. 2.5 ：

1 Pin Configuration(SOT-26)

2 Pin Description(SOT-26)

3 Absolute Maximum Rating Maximum supply voltage 5.5V

Maximum voltage on any pin VDD+0.3 V Maximum current on any PAD 100mA Continuous Power Dissipation 200mW Storage Temperature -50 ~ 150℃

Operating Temperature -20 ~ 75℃ Junction Temperature 150℃

Note 2 : Unless any other command is noted, all above are operated in normal temperature.

4 ESD & Latch-up Characteristics

5 Electrical Characteristics

▪ VDD=3.3V, Typical system frequency (Unless otherwise noted), TA = 25℃

Note 3: The sensitivity can be increased with lower CS value. The recommended value of CS is 10pF when using 3T PC(Poly Carbonate) cover and 10 ㎜ x 7 ㎜

touch pattern and middle sensitivity selection.

Note 4: CR value is recommended as same that of CS_TOT as possible for effective differential sensitivity calibration. CS_TOT = CS + CPARA (CPARA is parasitic capacitance of CS pin)

If proper CR capacitor value is used, CR pin has almost same frequency as that of CS pin.

6 TS01S Implementation 6.1 Current consumption

TS01S uses internal bias circuit, so internal clock frequency and current consumption is not adjusted. The

typical current consumption curve of TS01S is represented in accordance with VDD voltage as below. The higher VDD requires more current consumption.

Internal bias circuit can make the circuit design simple and reduce external components.

Typical current consumption curve of TS01S

6.2 CS and CR implementatio

The parallel capacitor CS is added to CS and CR to CR to adjust fine sensitivity. The major factor of the

sensitivity is CS. The sensitivity would be increased when smaller CS value is used. (Ref. below Sensitivity

Example Figure) The CR value should be almost the same as the total CS capacitance (CS_TOT) for effective

differential sensitivity calibration. The total CS capacitance is composed of CS which is set for optimal

sensitivity and parasitic capacitance of CS pattern (CPARA). The parasitic capacitance of CS pattern is about 2pF if normal touch pattern size is used. But in the case of using larger touch pattern, CPARA is bigger than normal value.

The RS is serial connection resistor to avoid malfunction from external surge and ESD. (It might be optional.)

From 200Ω to 1kΩ is recommended for RS. The size and shape of touch PAD might have influence on the

sensitivity. The sensitivity will be optimal when the size of PAD is approximately an half of the first knuckle

(it’s about 10 ㎜ｘ 7 ㎜). The connection line of CS to the touch PAD is recommended to be routed as short as

possible to prevent from abnormal touch detection caused by connection line.

Sensitivity example figure of TS01S (when normal sensitivity selection selected)

6.3 SYNC implementation

From two TS01S to ten TS01S (or other TS series touch sensor) can work on the one application at the same time thanks to SYNC function with this pin. The SYNC pulse prevents over two sensing signal from interfering with each other. During the sense disenable period and SYNC input becomes high, internal clock is suspended. The RSYNC is pull-down resistor of SYNC pin. Too big value of RSYNC makes the SYNC pulse falling delay, and too small value of RSYNC makes rising delay. The typical value of RSYNC is 2MΩ.

TS01S has high sensitivity when SYNC is implemented as above figure (connect RSYNC between SYNC and GND). 6.4 SYNC implementation for sensitivity selection

Another function of SYNC pin of TS01S is the selection of sensitivity without any additional external component. The SYNC implementation for sensitivity selection is informed as below chart.

6.5 OUTPUT implementation

The OUT is an open drain structure. For this reason, the connection of pull-up resistor ROUT is required between OUT and VDD or another lower voltage node. When ROUT is connected to higher voltage node than VDD, the output current passes through protection diode to VDD and abnormal operation may be occurred.

The maximum output sink current is 4mA, so over a few kΩ must be used as ROUT. Normally 10kΩ is used as ROUT. The OUT is high in normal situation, and the value is low when a touch is detected on CS.

6.6 Internal reset operation

The TS01S has stable internal reset circuit that offers reset pulse to digital block. The supply voltage for a system start or restart should be under 0.3∙VDD of normal operation VDD. No external components required for TS01S power reset, thus it helps simple circuit design and minimize the cost ofapplication. CAUTION: The VDD rising time should be less then 100ms for proper power on reset.

7 Recommended Circuit Diagram 7.1 Application Example

1、The capacitor and resistor might be connected with CS (pin4) for getting a stable sensitivity.

2、The capacitor value which is connected to CR pin (CR) should be almost the same as the total CS capacitance (include parasitic capacitance) for an effective differential sensitivity calibration.

3、TS01S is reset by internal reset circuit. VDD voltage rising time should be shorter than 100msec for proper operation. 4、The sensitivity can be adjusted through a connection of SYNC pin. (Refer to chapter 6.4)

5、From two TS01S to ten TS01S (or other TS series touch sensor) can work on the one application at the same time thanks to SYNC function. (Refer to chapter 6.3)

6、TS01S OUT port has an open drain structure. The pull-up resistor should therefore be needed as above figure. 7、VDD periodic voltage ripples over 50mV or the ripple frequency which is lower than 10 kHz it can cause wrong sensitivity calibration. To prevent above problem, power (VDD, GND) line of touch circuit should be separated from the other circuit. Especially the LED driver power line or digital switching circuit power line should be certainly treated to be separated from touch circuit.

8、The CS pattern should be routed as short as possible and the width of the line should be around 0.25mm.

9、The CS pattern routing should be formed by bottom metal (opposite metal of touch PAD).

10、The capacitor which is between VDD and GND is an obligation. It should be placed as close as possible from TS01S. 11、The empty space of PCB must be filled with GND pattern to strengthen GND pattern and to prevent external noise that causes interference with the sensing frequency.

7.2 Example – Power Line Split Strategy PCB Layout A. Not split power Line (Bad power line design)

8 PACKAGE Description 8.1 Mechanical Drawing

NOTE:

1. Dimensions and tolerances are as per ANSI Y14.5, 1982. 2. Package surface to be matte finish VDI 11 ~ 13.

3. Die is facing up for mold. Die is facing down for trim/form, ie. Reverse trim/form.

4. The footlength measuring is based on the gauge plane method. 5. Dimension is exclusive of mold flash and gate burr.

6. Dimension is exclusive of solder plating. 7. All dimensions are mm. 8.2 Marking Description

NOTES:

LIFE SUPPORT POLICY

AD SEMICONDUCTOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF AD SEMICONDUCTOR CORPORATION

The ADS logo is a registered trademark of ADSemiconductor ⓒ 2006 ADSemiconductor – All Rights Reserved

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