ATA6824_08资料

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Features

•PWM and Direction-controlled Driving of Four Externally-powered NMOS Transistors•High Temperature Capability up to 200°C Junction

•A Programmable Dead Time Is Included to Avoid Peak Currents Within the H-bridge•Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply the Gate of the External Battery Reverse Protection NMOS•5V/3.3V Regulator and Current Limitation Function•Reset Derived From 5V/3.3V Regulator Output Voltage•A Programmable Window Watchdog

•Battery Overvoltage Protection and Battery Undervoltage Management•Overtemperature Warning and Protection (Shutdown)•High Voltage Serial Interface for Communication•

QFN32 Package

1.Description

The ATA6824 is designed for DC motor control application in automotive high temper-ature environment like in mechatronic assemblies in the vicinity of the hot engine, e.g.turbo charger. With a maximum junction temperature of 200°C, ATA6824 is suitablefor applications with an ambient temperature up to 150°C.

The IC includes 4 driver stages to control 4 external power MOSFETs. An externalmicrocontroller provides the direction signal and the PWM frequency. In PWM opera-tion, the high-side switches are permanently on while the low-side switches areactivated by the PWM frequency. ATA6824 contains a voltage regulator to supply themicrocontroller; via the input pin VMODE the output voltage can be set to 5V or 3.3Vrespectively.

The on-chip window watchdog timer provides a pin-programmable time window. Thewatchdog is internally trimmed to an accuracy of 10% SPI with a maximum data rateof 20kBaud.

High Temperature H-bridge Motor DriverATA6824 4931E–AUTO–01/08Figure 1-1.Block Diagram

MCVRESCPVRESCPLORGATEH2RGATEH1S1S2RGATEL1RGATEL2PGNDGNDChargePumpCPIHOT12VRegulatorUVOTP12 bitOVSupervisorDG2DG1CCHS Driver 2HS Driver 1LS Driver 1LS Driver 2VBATDG3CCPCVGVBATVGPBATVINTVint 5VRegulatorLogic ControlOscillatorCC timerCCCRCCRRWDCVINTCPWD timerTP1VBATVBGSerial InterfaceVBATSWVCC 5VRegulatorSIOBandgapCSIOWDTP2DIRPWMRXTXVCCVMODE/RESETCVCCBatteryMicrocontroller2

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2.Pin Configuration

Figure 2-1.

Pinning QFN32

TP2VBATSWVBATVCCPGNDL1L2PBATVMODEVINTRWDCC/RESETWDGNDSIO 32 31 30 29 28 27 26 25124232223Atmel YWW421ATA6824205ZZZZZ-AL196718817 9 10 11 12 13 14 15 16TXDIRPWMTP1RXDG3DG2DG1VGCPLOCPHIVRESH2S2H1S1Note:

YWW Date code (Y = Year - above 2000, WW = week number)ATA6824 Product nameZZZZZ Wafer lot numberAL Assembly sub-lot number

Table 2-1.

Pin1234567101112131415161718192021

Pin Description

SymbolVMODEVINTRWDCC/RESETWDGNDSIOTXDIRPWMTP1RXDG3DG2DG1S1H1S2H2VRES

I/OII/OII/OOIII/OIII–OOOOI/OOI/OOI/O

Function

Selector for VCC and interface logic voltage levelBlocking capacitor 220 nF/10V/X7RResistor defining the watchdog intervalRC combination to adjust cross conduction timeReset signal for microcontrollerWatchdog trigger signalGround for chip core

High Voltage (HV) serial interface

Transmit signal to serial interface from microcontrollerDefines the rotation direction for the motorPWM input controls motor speedTest pin to be connected to GND

Receive signal from serial interface for microcontrollerDiagnostic output 3Diagnostic output 2Diagnostic output 1

Source voltage H-bridge, high-side 1Gate voltage H-bridge, high-side 1Source voltage H-bridge, high-side 2Gate voltage H-bridge, high-side 2

Gate voltage for reverse protection NMOS, blocking capacitor 470 nF/25V/X7R

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Table 2-1.

Pin2223242526272829303132

Pin Description (Continued)

SymbolCPHICPLOVGPBATL2L1PGNDVCCVBATVBATSWTP2

I/OIOI/OIOOIOIO–

Function

Charge pump capacitor 220 nF/25V/X7RBlocking capacitor 470 nF/25V/X7R

Power supply (after reverse protection) for charge pump and H-bridgeGate voltage H-bridge, low-side 2Gate voltage H-bridge, low-side 1

Power ground for H-bridge and charge pump

5V/100 mA supply for microcontroller, blocking capacitor 2.2 µF/10V/X7RSupply voltage for IC core (after reverse protection)100Ω PMOS switch from VBATTest pin to be connected to GND

3.General Statement and Conventions

•Parameter values given without tolerances are indicative only and not to be tested in production

•Parameters given with tolerances but without a parameter number in the first column of parameter table are “guaranteed by design” (mainly covered by measurement of other

specified parameters). These parameters are not to be tested in production. The tolerances are given if the knowledge of the parameter tolerances is important for the application•The lowest power supply voltage is named GND

•All voltage specifications are referred to GND if not otherwise stated

•Sinking current means that the current is flowing into the pin (value is positive)•Sourcing current means that the current is flowing out of the pin (value is negative)

3.1Related Documents

•Qualification of integrated circuits according to Atmel® HNO procedure based on AEC-Q100 •AEC-Q100-004 and JESD78 (Latch-up)•ESD STM 5.1-1998

•CEI 801-2 (only for information regarding ESD requirements of the PCB)

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4.Application

4.1

General Remark

This chapter describes the principal application for which the ATA6824 was designed. BecauseAtmel cannot be considered to understand fully all aspects of the system, application and envi-ronment, no warranties of fitness for a particular purpose are given.Table 4-1.

CVINTCVCCCCCRCCCVGCCPCVRESRRWDCSIO

Typical External Components (See also Figure 1-1 on page 2)

Value

220nF, 10V, X7R2.2µF, 10V, X7R

Typical 330pF, 100V, COGTypical 10 kΩ470nF, 25V, X7R220nF, 25V, X7R470nF, 25V, X7RTypical 51kΩTypical 220 pF, 100V

10%10%10%1%10%Tolerance10%10%

Blocking capacitor at VINTBlocking capacitor at VCC

Cross conduction time definition capacitorCross conduction time definition resistorBlocking capacitor at VGCharge pump capacitorReservoir capacitor

Watchdog time definition resistorFilter capacitor for serial interface

Component Function5.Functional Description

5.1

5.1.1

Power Supply Unit with Supervisor Functions

Power Supply

The IC is supplied by a reverse-protected battery voltage. To prevent it from destruction, properexternal protection circuitry has to be added. It is recommended to use at least a capacitor com-bination of storage and HF caps behind the reverse protection circuitry and closed to the VBATpin of the IC (see Figure 1-1 on page 2).

An internal low-power and low drop regulator (VINT), stabilized by an external blocking capacitor,provides the necessary low-voltage supply for all internal blocks except the digital IO pins. Thisvoltage is also needed in the wake-up process. The low-power band gap reference is trimmedand is used for the bigger VCC regulator, too. All internal blocks are supplied by the internalregulator.

Note:

The internal supply voltage VINT must not be used for any other supply purpose!

Nothing inside the IC except the logic interface to the microcontroller is supplied by the 5V/3.3VVCC regulator.

A power-good comparator checks the output voltage of the VINT regulator and keeps the wholechip in reset as long as the voltage is too low.

There is a high-voltage switch which brings out the battery voltage to the pin VBATSW for mea-surement purposes. This switch is switched ON for VCC = HIGH and stays ON in case of awatchdog reset. The signal can be used to switch on external voltage regulators, etc.

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5.1.2

Voltage Supervisor

This block is intended to protect the IC and the external power MOS transistors against overvolt-age on battery level and to manage undervoltage on it.

Function: in case of both overvoltage alarm (VTHOV) and of undervoltage alarm (VTHUV) the exter-nal NMOS motor bridge transistors will be switched off. The failure state will be flagged via DG2.No other actions will be carried out. The voltage supervision block is connected to VBAT and fil-tered by a first-order low pass with a corner frequency of typical 15kHz.

5.1.3

Temperature Supervisor

There is a temperature sensor integrated on-chip to prevent the IC from overheating due to afailure in the external circuitry and to protect the external NMOSFET transistors.

In case of detected overtemperature (180°C), the diagnostic pin DG3 will be switched to “H” tosignalize this event to the microcontroller. It should undertake actions to reduce the power dissi-pation in the IC. In case of detected overtemperature (200°C), the VCC regulator and all driversincluding the serial interface will be switched OFF immediately and /RESET will go LOW. Both temperature thresholds are correlated. The absolute tolerance is ±15°C and there is abuilt-in hysteresis of about 10°K to avoid fast oscillations. After cooling down below the 170°Cthreshold; the IC will go into Active mode.

5.25V/3.3V VCC Regulator

The 5V/3.3V regulator is fully integrated on-chip. It requires only a 2.2µF ceramic capacitor forstability and has 100mA current capability. Using the VMODE pin, the output voltage can beselected to either 5V or 3.3V. Switching of the output voltage during operation is not intended tobe supported. The VMODE pin must be hard-wired to either VINT for 5V or to GND for 3.3V. Thelogic HIGH level of the microcontroller interface will be adapted to the VCC regulator voltage.The output voltage accuracy is in general < ±3%; in the 5V mode with VVBAT < 8V it is limited to<5%.

To prevent destruction of the IC, the current delivered by the regulator is limited to maximum160mA to 320mA. The delivered voltage will break down and a reset may occur.

Please note that this regulator is the main heat source on the chip. The maximum output currentat maximum battery voltage and high ambient temperature can only guaranteed if the IC ismounted on an efficient heat sink.

A power-good comparator checks the output voltage of the VCC regulator and keeps the exter-nal microcontroller in reset as long as the voltage is too low.

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Figure 5-1.

Correlation between VCC Output Voltage and Reset Threshold

5.15V4.9V4.85VVCC1VtHRESH4.1VVCC1-VtHRESH = VCC1 - VtHRESHThe voltage difference between the regulator output voltage and the upper reset threshold volt-age is bigger than 100mV.

5.3Reset and Watchdog Management

The timing basis of the watchdog is provided by the trimmed internal oscillator. Its period TOSC isadjustable via the external resistor RWD.

The watchdog expects a triggering signal (a rising edge) from the microcontroller at the WDinput within a period time window of TWD.

Figure 5-2.Timing Diagram of the Watchdog Function

trestresshort/RESETtdt1t2t1t2tdWD7

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5.3.1

Timing Sequence

For example, with an external resistor RWD=33kΩ ±1% we get the following typical parametersof the watchdog.

TOSC=12.32µs, t1=12.1ms, t2=9.61ms, TWD=16.88ms±10%

The times tres=68ms and td=68ms are fixed values with a tolerance of 10%.

After ramp-up of the battery voltage (power-on reset), the VCC regulator is switched on. Thereset output, /RESET, stays low for the time tres (typically 68ms), then switches to high. For aninitial lead time td (typically 68ms for setups in the controller) the watchdog waits for a risingedge on WD to start its normal window watchdog sequence. If no rising edge is detected, thewatchdog will reset the microcontroller for tres and wait td for the rising edge on WD.

Times t1 (close window) and t2 (open window) form the window watchdog sequence. To avoidreceiving a reset from the watchdog, the triggering signal from the microcontroller must hit thetimeframe of t2=9.61ms. The trigger event will restart the watchdog sequence.Figure 5-3.

TWD versus RWD

6050maxtypTWD (ms)4030min20100102030405060708090100RWD (kΩ)If triggering fails, /RESET will be pulled to ground for a shortened reset time of typically 2ms.The watchdog start sequence is similar to the power-on reset.

The internal oscillator is trimmed to a tolerance of < ±10%. This means that t1 and t2 can alsovary by ±10%. The following calculation shows the worst case calculation of the watchdogperiod Twd which the microcontroller has to provide. t1min = 0.90 × t1 = 10.87 ms, t1max = 1.10 × t1 = 13.28mst2min = 0.90 × t2 = 8.65ms, t2max = 1.10 × t2 = 10.57msTwdmax = t1min + t2min = 10.87ms + 8.65ms = 19.52ms Twdmin = t1max = 13.28ms

Twd = 16.42ms ±3.15ms (±19.1%)

Figure 5-3 on page 8 shows the typical watchdog period TWD depending on the value of theexternal resistor ROSC.

A reset will be active for VCC < VtHRESx; the level VtHRESx is realized with a hysteresis (HYSRESth).

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5.4

High Voltage Serial Interface

A bi-directional bus interface is implemented for data transfer between hostcontroller and thelocal microcontroller (SIO).

The transceiver consists of a low side driver (1.2V at 40mA) with slew rate control, wave shap-ing, current limitation, and a high-voltage comparator followed by a debouncing unit in thereceiver. In case of an active reset shown at pin /RESET the pin SIO is switched to low.

5.4.1

Transmit Mode

During transmission, the data at the pin TX will be transferred to the bus driver to generate a bussignal on pin SIO. The pin TXD has a pull-down resistor included.

To minimize the electromagnetic emission of the bus line, the bus driver has an integrated slewrate control and wave-shaping unit. Transmission will be interrupted in the following cases:•Thermal shutdown active

Figure 5-4.

Definition of Bus Timing Parameters

tBitTXD(input to transmitting Node)tBittBittBus_dom(max)tBus_rec(min)THRec(max)VS(Transceiversupplyof transmittingnode)THDom(max)SIO Bus SignalTHRec(min)THDom(min)Thresholds ofreceiving node 1Thresholds ofreceiving node 2tBus_dom(min)RXD(output of receiving Node 1)tBus_rec(max)trx_pdf(1)RXD(output of receiving Node 2)trx_pdr(1)trx_pdr(2)trx_pdf(2)The recessive BUS level is generated from the integrated 30kΩ pull-up resistor in series with anactive diode. This diode prevents the reverse current of VBUS during differential voltagebetween VSUP and BUS (VBUS>VSUP).

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5.5

5.5.1

Control Inputs DIR and PWM

Pin DIR

Logical input to control the direction of the external motor to be controlled by the IC. An internalpull-down resistor is included.

5.5.2Pin PWM

Logical input for PWM information delivered by external microcontroller. Duty cycle and fre-quency at this pin are passed through to the H-bridge. An internal pull-down resistor is included.Table 5-1.

ON011

DIRX01

Status of the IC Depending on Control Inputs and Detected Failures

Driver Stage for External Power MOSH1OFFON/PWM

L1OFFOFFPWM

H2OFF/PWMON

L2OFFPWM OFF

Standby modeMotor PWM forwardMotor PWM reverse

XPWMPWM

Comments

PWM

Control Inputs

The internal signal ON is high when

•At least one valid trigger has been accepted (SYNC=1)•VBAT is inside the specified range (UV=0 and nOV=1)

•The charge pump has reached its minimum voltage (CPOK=1) and •The device is not overheated (OT2=0)

In case of a short circuit, the appropriate transistor is switched off after a debounce time of about10µs. In order to avoid cross current through the bridge, a cross conduction timer is imple-mented. Its time constant is programmable by means of an RC combination.Table 5-2.

CPOK0XXXXNote:Status of the Diagnostic Outputs

Device StatusOT1X1XX

OVXX1X

UVXXX1

SCXXXX

Diagnostic OutputsDG1––––

DG21–11–

DG3–1–––

Charge pump failureOvertemperature warning

OvervoltageUndervoltageShort circuitComments

XXX11 X represents: don't care – no effect)OT1: Overtemperature warningOV: Overvoltage of VBATUV: Undervoltage of VBATSC: Short circuit

CPOK: Charge pump OK

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5.6

VG Regulator

The VG regulator is used to generate the gate voltage for the low-side driver. Its output voltagewill be used as one input for the charge pump, which generates the gate voltage for thehigh-side driver. The purpose of the regulator is to limit the gate voltage for the external powerMOS transistors to 12V. It needs a ceramic capacitor of 470nF for stability. The output voltageis reduced if the supply voltage at VBAT falls below 12V.

5.7Charge Pump

The integrated charge pump is needed to supply the gates of the external power MOS transis-tors. It needs a shuffle capacitor of 220nF and a reservoir capacitor of 470nF. Without load, theoutput voltage on the reservoir capacitor is VBAT plus VG. The charge pump is clocked with adedicated internal oscillator of 100KHz. The charge pump is designed to reach a good EMClevel.

5.8Thermal Shutdown

There is a thermal shutdown block implemented. With rising junction temperature, a first warninglevel will be reached at 180°C. At this point the IC stays fully functional and a warning will besent to the microcontroller. At junction temperature 200°C the VCC regulator will be switched offand a reset occurs.

5.9H-bridge Driver

The IC includes two push-pull drivers for control of two external power NMOS used as high-sidedrivers and two push-pull drivers for control of two external power NMOS used as low-side driv-ers. The drivers are able to be used with standard and logic-level power NMOS.

The drivers for the high-side control use the charge pump voltage to supply the gates with a volt-age of VG above the battery voltage level. The low-side drivers are supplied by VG directly. It ispossible to control the external load (motor) in the forward and reverse direction (see Table 5-1on page 10). The duty cycle of the PMW controls the speed. A duty cycle of 100% is possible inboth directions.

5.9.1

Cross Conduction Time

To prevent high peak currents in the H-bridge, a non-overlapping phase for switching the exter-nal power NMOS is realized. An external RC combination defines the cross conduction time inthe following way:

tCC (µs) = 0.41 × RCC (kΩ) × CCC (nF) (tolerance: ±5% ±0.15 µs)

The RC combination is charged to 5V and the switching level of the internal comparator is 67%of the start level.

The resistor RCC must be greater than 5 kΩ and should be as close as possible to 10 kΩ, the CCCvalue has to be ≤ 5nF. Use of COG capacitor material is recommended. The time measurement is triggered by the PWM or DIR signal crossing the 50% level.

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Figure 5-5.Timing of the Drivers

PWM orDIR50%ttLxHLtLxftLxLHtLxr80%Lx20%tCCttHxLHtHxrtHxHLtHxftCC80%Hx20%tThe delays tHxLH and tLxLH include the cross conduction time tCC.

5.10Short Circuit Detection

To detect a short in H-bridge circuitry, internal comparators detect the voltage differencebetween source and drain of the external power NMOS. If the transistors are switched ON andthe source-drain voltage difference is higher than the value VSC (4V with tolerances) for a time>tSC (typically 10µs) the signal SC (short circuit) will be set and the drivers will be switched offimmediately. The diagnostic pin DG1 will be set to “H”. With the next transition on pin PWM, thebit will be cleared and the corresponding drivers, depending on the DIR pin, will be switched onagain.

There is a PBAT supervision block implemented to detect the possible voltage drop on PBATduring a short circuit. If the voltage at PBAT falls under VSCPB (5.6V with tolerances) for a time>tSC the drivers will be switched off immediately and DG1 will be set to “H”. It will be cleared asabove.

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6.Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Pin DescriptionGroundPower ground

Reverse protected battery voltageReverse protected battery voltageDigital outputDigital output

4.9V output, external blocking capacitorCross conduction time capacitor/resistor combination

Digital input coming from microcontrollerWatchdog timing resistorDigital input direction control

Digital input PWM control + Test mode5V regulator outputDigital input

12V output, external blocking capacitorDigital outputDigital input

Serial interface data pin

Source external high-side NMOSGates external low-side NMOSGates of external high-side NMOSCharge pumpCharge pumpCharge pump outputSwitched VBATPower dissipationStorage temperatureSoldering temperature (10s)Notes:

1.For VVBAT ≤13.5V

2.May be additionally limited by external thermal resistance

Pin NameGNDPGNDVBATPBAT/RESETDG1, DG2, DG3

VINTCCWDRWDDIRPWMVCCVMODEVGRXTXSIOS1, S2L1, L2H1, H2CPLOCPHIVRESVBATSWPtotϑSTOREϑSOLDERING

–55Min0–0.3–0.3–0.3–0.3–0.3–0.3–0.3–0.3–0.3–0.3–0.3–0.3–0.3–0.3–0.3–0.3–27(1)–2VPGND – 0.3VS – 1–0.3–0.3–0.3–0.3

Max0+0.3+40+40VVCC + 0.3VVCC + 0.3+5.5VVCC + 0.3VVCC + 0.3VVCC + 0.3VVCC + 0.3VVCC + 0.3+5.5VVINT + 0.3+16VVCC + 0.3VVCC + 0.3VVBAT + 2+30VVG + 0.3VS + 16VPBAT + 0.3VVRES + 0.3

+30VVBAT + 0.31.4(2)+200240

UnitVVVVVVVVVVVVVVVVVVVVVVVVVW°C°C

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7.Thermal Resistance

Parameters

Thermal resistance junction to heat slug

Thermal resistance junction to ambient when heat slug is soldered to PCB

SymbolRthjcRthja

Value<525

UnitK/WK/W

8.Operating Range

The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied unless otherwise stated explicitly.Parameters

Operating supply voltage(1)Operating supply voltage(2)Operating supply voltage(3)Operating supply voltage(4)Operating supply voltage(5)

Junction temperature range under biasNormal functionality

Normal functionality, overtemperature warningDrivers for H1, H2, L1, L2, and SIO are switched OFF, VCC regulator is OFFNote:

1.Full functionality

2.H-bridge drivers may be switched off (undervoltage detection)

3.H-bridge drivers are switched off, 5V/3.3V regulator with reduced parameters, RESET works correctly4.H-bridge drivers are switched off, 5V regulator not working, RESET not correct5.H-bridge drivers are switched off

SymbolVVBAT1VVBAT2VVBAT3VVBAT4VVBAT5TjTaTaTa

Min7.50> 20–40–40180

Max18<7< 6<4.0+200+150200

UnitV VVVV °C°C°C°C

200 220

9.Noise and Surge Immunity

Parameters

Conducted interferencesInterference suppressionESD (Human Body Model)CDM (Charge Device Model)Note:

1.Test pulse 5: Vvbmax = 40V

Test ConditionsISO 7637-1IEC-CISPR25ESD S 5.1ESD STM5.3.

ValueLevel 4(1)Level 52 kV500V

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10.Electrical Characteristics

All parameters given are valid for 7V ≤VBAT ≤18V and for –40°C ≤ϑambient ≤150°C unless stated otherwise.No.ParametersTest ConditionsPinSymbolMinTypMax1Power Supply and Supervisor Functions25, 30IVBAT171.1Current consumption VBATVVBAT = 13.5V(1)1.2Internal power supply2VINT4.84.945.11.2351.3Band gap voltageVBG

Overvoltage threshold 1.430VTHOV19.822.3

VBAT

Overvoltage threshold 30VTOVhys121.5

hysteresis VBAT

Undervoltage threshold 30VTHUV6.571.6

VBAT

Undervoltage threshold Measured during 0.20.430VTUVhys1.7

qualification only hysteresis VBAT

On resistance of VBAT 31RON_VBATSW100VVBAT = 13.5V1.8

switch

25V/3.3V Regulator9V < VVBAT < 40V, 2.1Regulated output voltage 4.85 (3.2)5.15 (3.4)29VCC1

Iload = 0 mA to 100 mA9V < VVBAT < 40V, 2.1aRegulated output voltage Iload = 0 mA to 80 mA,29VCC14.85 (3.2)5.15 (3.4)

Ta > 125°C

6V < VVBAT ≤9V2.2Regulated output voltage 4.75 (3.2)5.25 (3.4)29VCC2

Iload = 0 mA to 100 mA

DC line 29<1502.3Line regulationIload = 0 mA to 100 mA

regulationDC load 2.4Load regulationIload = 0 mA to 100 mA29<1050

regulation

2.5Output current limitationVVBAT > 6V29IOS1100300Serial inductance to CVCC

2.629ESL120

including PCB

Serial resistance to CVCC

29ESR00.52.7

including PCB

(2), (3)29CVCC1.53.02.8Blocking cap at VCC2.9HIGH threshold VMODE 1VMODE H4.02.10LOW threshold VMODE1VMODE L0.7* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameterNotes:1.DIR, PWM = high

2.The use of X7R material is recommended

3.For higher values, stability at zero load is not guaranteed 4.Tested during qualification only

5.Value depends on T100; function tested with digital test pattern 6.Tested during characterization only 7.Supplied by charge pump

8.See section “Cross Conduction Time”

9.Voltage between source-drain of external switching transistors in active case 10.The short-circuit message will never be generated for switch-on time < tsc11.See Figure 5-4 on page 9 “Definition of Bus Timing Parameters”

UnitmAVVVVVVΩ

Type*AAAAAAAA

VVVmVmVmAnHΩµFVVAAAAACDDDAA15

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10.Electrical Characteristics (Continued)

All parameters given are valid for 7V ≤VBAT ≤18V and for –40°C ≤ϑambient ≤150°C unless stated otherwise.No.ParametersTest ConditionsPinSymbolMinTypMax3VG RegulatorV = PBAT = 14V 24VVG3.1Regulated output voltage BAT11.913

Imax = 20 mA

V = PBAT = 9V 24VVG7.09.03.2Regulated output voltage BAT

Imax = 20 mA

4Reset and WatchdogVCC threshold voltage VMODE = “H” 4.14.9 (3.25)29VtHRESH

level for /RESET(VMODE = “L”) Tracking of reset 100 VMODE = “H”

4.1athres-hold with regulated 29VVCC1-VtHRESH

(70)(VMODE = “L”)

output voltage

VMODE = “H” VCC threshold voltage 29VtHRESL4.3 (2.86)4.2

level for /RESET(VMODE = “L”)

350Hysteresis of /RESET VMODE = “H” 29HYSRESth700.24.3(4)

(220)level(VMODE = “L”)

Length of pulse at (5)

5tres68004.4

/RESET pin

Length of short pulse at (5)

5tresshort2004.5

/RESET pin

Wait for the first WD (5)

5td68004.6

trigger

Time for VCC < VtHRESL (4)

29tdelayRESL0.524.7

before activating /RESETResistor defining internal 4.8bias currents for watchdog 3RRWD1091

oscillator

Watchdog oscillator 4.9RRWD = 33 kΩ3TOSC11.0913.55

period

Watchdog oscillator 16244.10period with internal TOSC_start

resistor

0.3 × Watchdog input 4.116VILWD

VVCClow-voltage threshold

0.7 × Watchdog input 4.126VIHWD

VVCChigh-voltage threshold

* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameterNotes:1.DIR, PWM = high

2.The use of X7R material is recommended

3.For higher values, stability at zero load is not guaranteed 4.Tested during qualification only

5.Value depends on T100; function tested with digital test pattern 6.Tested during characterization only 7.Supplied by charge pump

8.See section “Cross Conduction Time”

UnitVV

Type*AA

VmVVVT100T100T100µskΩµsµsVV

AAAAAAACDAAAA

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10.Electrical Characteristics (Continued)

All parameters given are valid for 7V ≤VBAT ≤18V and for –40°C ≤ϑambient ≤150°C unless stated otherwise.No.ParametersTest ConditionsPinSymbolMinTypMaxHysteresis of watchdog 4.1316VhysWD

input voltage threshold

980 × (5)

t14.14Close window

TOSC780 × (5)

t24.15Open window

TOSC

Output low-voltage of 5VOLRES0.44.16At IOLRES = 1 mA

/RESET

Internal pull-up resistor at 510 1.175RPURES

pin /RESET

5High Voltage Serial InterfaceNormal mode; 5.1Low-level output current13ILRX4

VSIO=0V, VRX=0.4V

Normal mode; VSIO=VBAT

13IHRX45.2High-level output current

VRX=VCC–0.4V

0.9 × Driver recessive output 8VSIOrec5.3VTXD = 0V; ISIO = 0 mA

VBATvoltage

Driver dominant voltageVVAT = 7.3V8V_LoSUP5.41.2

Rload = 500ΩVBUSdom_DRV_LoSUP

Driver dominant voltageVVAT = 18V8V_HiSUP25.5

Rload = 500ΩVBUSdom_DRV_HiSUP

Driver dominant voltageVVAT = 7.3V8V_LoSUP_1k0.65.6

Rload = 1000ΩVBUSdom_DRV_LoSUP

Driver dominant voltageVVAT = 18V0.85.78V_HiSUP_1k_

Rload = 1000ΩVBUSdom_DRV_HiSUP

The serial diode is 2030605.8Pull up resistor to VS8RLIN

mandatory

5.9Current limitationVBUS = VBAT_max8IBUS_LIM50250Input leakage current at Input leakage currentthe receiver including driver off

–15.108ISIO_PAS_dom

pull-up resistor as VSIO = 0V

VBAT = 12Vspecified

Driver offLeakage current SIO 8V < VBAT < 18V5.118ISIO_PAS_rec30

recessive8V < VSIO < 18V

VSIO ≥ VBAT

* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameterNotes:1.DIR, PWM = high

2.The use of X7R material is recommended

3.For higher values, stability at zero load is not guaranteed 4.Tested during qualification only

5.Value depends on T100; function tested with digital test pattern 6.Tested during characterization only 7.Supplied by charge pump

8.See section “Cross Conduction Time”

UnitV

Type*AAA

VkΩ

mAmAVVVVVkΩmAmA

DDAAAAADAA

µAA

4931E–AUTO–01/08

10.Electrical Characteristics (Continued)

All parameters given are valid for 7V ≤VBAT ≤18V and for –40°C ≤ϑambient ≤150°C unless stated otherwise.No.ParametersTest ConditionsPinSymbolMinTypMaxLeakage current at ground loss

Control unit disconnected GNDDevice = VS

8ISIO_NO_gnd5.12from groundVBAT =12V–11

Loss of local ground must 0V < VSIO < 18Vnot affect communication in the residual networkNode has to sustain the current that can flow VBAT disconnected

1005.13under this condition. Bus VSUP_Device = GND8ISIO

must remain operational 0V < VSIO < 18Vunder this conditionCenter of receiver VSIO_CNT = 8VSIO_CNT5.140.475VS0.5VS0.525VS

(Vth_dom+Vth_rec)/2threshold

5.15Receiver dominant stateVEN = 5V8VSIOdom0.4VS8VSIOrec0.6VS5.16Receiver recessive stateVEN = 5V5.17Receiver input hysteresisVHYS = Vth_rec – Vth_dom8VSIOhys0.1VS0.175VSTHRec(max) = 0.744 × VBATTHDom(max) = 0.581 × VBAT

5.18Duty cycle 18D10.380VBAT = 7.3V to 18V

tBit = 50 µs

D1 = tbus_rec(min) / 2 × tBit(11)THRec(min) = 0.422 × VBATTHDom(min) = 0.284 × VBAT

5.19Duty cycle 28D20.600VBAT = 7.3V to 18V

tBit = 50 µs

D2 = tbus_rec(max) / 2 × tBit(11)

Propagation delay of 5.208trx_pd6trec_pd = max(trx_pdr,trx_pdf)(11)

receiver

Symmetry of receiver 8trx_sym–2+25.21trx_sym = trx_pdr – trx_pdf(11)

propagation delay

6Control Inputs DIR, PWM, WD, TX0.3 × Input low-voltage 6.1VIL

VVCCthreshold

0.7 × Input high-voltage 6.2VIH

VVCCthreshold

(6)6.3HysteresisHYS0.7* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameterNotes:1.DIR, PWM = high

2.The use of X7R material is recommended

3.For higher values, stability at zero load is not guaranteed 4.Tested during qualification only

5.Value depends on T100; function tested with digital test pattern 6.Tested during characterization only 7.Supplied by charge pump

8.See section “Cross Conduction Time”

UnitType*mAA

µAA

VVVVAAAAA

µsµs

AAA18

ATA6824

4931E–AUTO–01/08

ATA6824

10.Electrical Characteristics (Continued)

All parameters given are valid for 7V ≤VBAT ≤18V and for –40°C ≤ϑambient ≤150°C unless stated otherwise.No.ParametersTest ConditionsPinSymbolMinTypMax6.4Pull-down resistorDIR, PWN, WD, TXRPD25501001006.5Rise/fall timetrf

7ChargePumpVVBAT

7.1Charge pump voltageLoad = 0A21VCP

+ VVG

Load = 3 mA, VVBAT

7.2Charge pump voltage21VCP

+ VVG – 1CCP = 100 nF

Period charge pump 9117.3T100

oscillator

CP load current in VG 1007.4Load = 0AIVGCPz

without CP load

CP load current in VG with Load = 3 mA, 3.37.5IVGCP

CP loadCCP = 100 nF8H-bridge DriverLow-side driver HIGH 8.1VLxHVVG

output voltage

ON-resistance of sink RDSON_LxL,

208.2

x = 1, 2stage of pins L1, L2

ON-resistance of source RDSON_LxH,

208.3

x = 1, 2stage of pins L1, L2

Output peak current at ILxL,

8.4pins L1, L2, switched to VLx = 3V100

x = 1, 2

LOW

Output peak current at ILxH,

8.5pins L1, L2, switched to VLx = 3V–100

x = 1, 2

HIGH

Pull-down resistance at RPDLx

301008.6

x = 1, 2pins L1, L2

ON-resistance of sink RDSON_HxL,

208.7VSx = 0

x = 1, 2stage of pins H1, H2

RDSON_HxH,ON-resistance of source 208.8VSx = VVBAT

x = 1, 2stage of pins H1, H2

VVBAT = 13.5V Output peak current at IHxL,

8.9VSx = VVBAT 100

pins Hx, switched to LOWx = 1, 2

VHx = VVBAT + 3V

* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameterNotes:1.DIR, PWM = high

2.The use of X7R material is recommended

3.For higher values, stability at zero load is not guaranteed 4.Tested during qualification only

5.Value depends on T100; function tested with digital test pattern 6.Tested during characterization only 7.Supplied by charge pump

8.See section “Cross Conduction Time”

UnitkΩnsVVµsµAmA

Type*DDAAADA

VΩΩmA

DAAD

mAkΩΩΩmA

DAAAD

4931E–AUTO–01/08

10.Electrical Characteristics (Continued)

All parameters given are valid for 7V ≤VBAT ≤18V and for –40°C ≤ϑambient ≤150°C unless stated otherwise.No.ParametersTest ConditionsPinSymbolMinTypMaxVVBAT = 13.5V Output peak current at IHxH,

–1008.10VSx = VVBAT

x = 1, 2pins Hx, switched to HIGH

VHx = VVBAT + 3V

Static high-side switch VSx = 0V VHxL,8.110.3

output low-voltage pins Hx IHx = 1 mAx = 1, 2Static high-side switch VVBAT + VVBAT + I = –10 µA

8.12output high-voltage pins LxVHxHstat1(7)

(PWM = static)VVG – 1VVG

H1, H2

Sink resistance between 310RHxsleep8.13Hx and ground in Sleep

mode

Dynamic ParametersDynamic high-side switch CHx = 5 nF VVBAT + VVBAT +

VHxHdyn18.14output high-voltage pins CCB = 100 nF

VVG – 1VVG

fPWM = 20 kHzH1, H2

Propagation delay time, Figure 5-5 on page 12

8.15low-side driver from high tLxHL0.5

VVBAT = 13.5V

to low

Propagation delay time, 0.5 + tCC8.16low-side driver from low to tLxLH

high

VVBAT = 13.5VtLxf8.17Fall time low-side driver0.5

CGx=5 nF

8.18Rise time low-side drivertLxr0.5Propagation delay time, Figure 5-5 on page 12

0.58.19high-side driver from high tHxHL

VVBAT = 13.5V

to low

Propagation delay time, 8.20high-side driver from low tHxLH0.5 + tCC

to high

VVBAT = 13.5V,8.21Fall time high-side driver0.5tHxf

CGx = 5 nF

8.22Rise time high-side drivertHxr0.5(8)tCC108.23Cross conduction time58.24External resistorRCC

58.25External capacitor CCC

* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameterNotes:1.DIR, PWM = high

2.The use of X7R material is recommended

3.For higher values, stability at zero load is not guaranteed 4.Tested during qualification only

5.Value depends on T100; function tested with digital test pattern 6.Tested during characterization only 7.Supplied by charge pump

8.See section “Cross Conduction Time”

UnitmAVV

Type*DDD

kΩD

µsA

µsµsµsµs

AAAA

µsµsµsµskΩnFAAAADD20

ATA6824

4931E–AUTO–01/08

ATA6824

10.Electrical Characteristics (Continued)

All parameters given are valid for 7V ≤VBAT ≤18V and for –40°C ≤ϑambient ≤150°C unless stated otherwise.No.ParametersTest ConditionsPinSymbolMinTypMaxR of tCC switching 8.26ON100RONCC

transistor

0.653 × 0.667 × 0.68 × Switching level of tCC 8.27Vswtcc

comparatorVVCCVVCCVVCCShort circuit detection (9)

VSC3.4.58.28

voltage

Short circuit detection (10)

tSC510158.29

time

9Diagnostic Outputs DG1, DG2, DG39.1Low level output current VDG = 0.4V(6)IL4IH49.2High level output currentVDG = VCC – 0.4V(6)* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameterNotes:1.DIR, PWM = high

2.The use of X7R material is recommended

3.For higher values, stability at zero load is not guaranteed 4.Tested during qualification only

5.Value depends on T100; function tested with digital test pattern 6.Tested during characterization only 7.Supplied by charge pump

8.See section “Cross Conduction Time”

UnitΩVVµsmAmAType*DDAADD21

4931E–AUTO–01/08

11.Ordering Information

Extended Type NumberATA6824-PHQW

PackageQFN32

RemarksPb-free

12.Package Information

Package: QFN 32 - 7 x 7 Exposed pad 4.7 x 4.7Dimensions in mmNot indicated tolerances ± 0.05 0.9±0.10.05-0.053212425321technical drawingsaccording to DINspecifications+074.780.30.617160.65 nom.4.5598Drawing-No.: 6.3-5097.01-4Issue: 1; 24.02.0322

ATA6824

4931E–AUTO–01/08

ATA6824

13.Revision History

Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document.Revision No.

History

• Section 5.2 “5V/3.3V VCC Regulator” on pages 6 to 7 changed• Section 5.4 “High Voltage Serial Interface” on page 9 changed

• Section 10 “Electrical Characteristics” numbers 4.1a and 4.3 on page 16 changed

• Put datasheet in a new template

• Section 1 “Description” on page 1 changed• Figure 1-1 “Block Diagram” on page 2 changed• Figure 2-1 “Pinning QFN32” on page 3 changed• Table 2-1 “Pin Description” on pages 3 to 4 changed• Table title Table 4-1 renamed

• Section 5.1.1 “Power Supply” on page 5 changed

• Section 5.1.3 “Temperature Supervisor” on page 6 changed

• Section 5.3 “Reset and Watchdog Management” on page 6 changed• Section 5.4 “High Voltage Serial Interface” on page 8 changed• Section 6 “Absolute Maximum Ratings” on page 13 changed• Section 8 “Operating Range” on page 14 changed

• Section 9 “Noise and Surge Immunity” on page 14 changed

• Section 10 “Electrical Characteristics” on pages 15 to 21 changed

4931E-AUTO-01/08

4931D-AUTO-04/07

4931E–AUTO–01/08

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4931E–AUTO–01/08

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