Philips SemiconductorsProduct specificationDual D-type flip-flop with set and reset74ALS74ADESCRIPTIONORDERING INFORMATIONThe 74ALS74 is a dual positive edge-triggered D-type flip-flopfeaturing individual data, clock, set, and reset inputs; also true andORDER CODEcomplementary outputs. Set (SD) and reset (RD) are asynchronousDESCRIPTIONCOMMERCIAL RANGEDRAWINGactive-Low inputs and operate independently of the clock input.VCC = 5V ±10%,NUMBERWhen set and reset are inactive (High), data at the D input isTamb = 0°C to +70°Ctransferred to the Q and Q outputs on the Low-to-High transition of14-pin plastic DIP74ALS74ANSOT27-1the clock. Data must be stable just one setup time prior to theLow-to-High transition of the clock for predictable operation. Clock14-pin plastic SO74ALS74ADSOT108-1triggering occurs at a voltage level and is not directly related to the14-pin plastic SSOPtransition time of the positive-going pulse. Following the hold timeType II74ALS74ADBSOT337-1interval, data at the D input may be changed without affecting thelevels of the output.PIN CONFIGURATIONTYPICALRD0114VCCTYPETYPICAL fMAXSUPPLY CURRENT(TOTAL)D0213RD174ALS74A150MHz3.0mACP0312D1SD0411CP1Q0510SD1Q069Q1GND78Q1SF00045INPUT AND OUTPUT LOADING AND FAN-OUT TABLEPINSDESCRIPTION74ALS (U.L.) LOAD VALUEHIGH/LOW HIGH/LOWD0, D1Data inputs1.0/2.020µA/0.2mACP0, CP1Clock inputs (active rising edge)1.0/2.020µA/0.2mASD0, SD1Set inputs (active-Low)2.0/4.040µA/0.4mARD0, RD1Reset inputs (active-Low)2.0/4.040µA/0.4mAQ0, Q1, Q0, Q1Data outputs20/800.4mA/8mANOTE:One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.LOGIC SYMBOLIEC/IEEE SYMBOL2124S&D0D1353CP02C14SD01D161RD0R11CP11010SD1S913RD111C2Q0Q0Q1Q1122D138RVCC = Pin 145698GND = Pin 7SF00046SF000471996 Jul 012853–1278 01670Philips SemiconductorsProduct specificationDual D-type flip-flop with set and reset74ALS74ALOGIC DIAGRAMFUNCTION TABLEINPUTSOUTPUTSOPERATINGSDRDCPDQQMODESD4, 10LHXXH LAsynchronous setHLXXLHAsynchronous resetRD1, 135, 9QLLXXHHUndetermined*HH↑hHLLoad “1”CP3, 116, 8QHH↑lLHLoad “0”HH↑XNCNCHoldD2, 12H=High voltage levelh=High state must be present one setup time prior toLow-to-High clock transitionVGND = Pin 7CC = Pin 14L=Low voltage levell=Low state must be present one setup time prior toSF00048Low-to-High clock transitionNC=No change from the previous setupX=Don’t care↑=Low-to-High clock transition↑=Not Low-to-High clock transition*=Both outputs will be High while both SD and RD are Low,but the output states are unpredictable if SD and RD goHigh simultaneouslyABSOLUTE MAXIMUM RATINGS(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)SYMBOLPARAMETERRATINGUNITVCCSupply voltage–0.5 to +7.0VVINInput voltage –0.5 to +7.0VIINInput current–30 to +5mAVOUTVoltage applied to output in High output state–0.5 to VCCVIOUTCurrent applied to output in Low output state16mATambOperating free-air temperature range0 to +70°CTstgStorage temperature range–65 to +150°CRECOMMENDED OPERATING CONDITIONSSYMBOLPARAMETERLIMITSMINNOMMAXUNITVCCSupply voltage4.55.05.5VVIHHigh-level input voltage2.0VVILLow-level input voltage0.8VIIkInput clamp current–18mAIOHHigh-level output current–0.4mAIOLLow-level output current 8mATambOperating free-air temperature range0 +70°C1996 Jul 013Philips SemiconductorsProduct specificationDual D-type flip-flop with set and reset74ALS74ADC ELECTRICAL CHARACTERISTICS(Over recommended operating free-air temperature range unless otherwise noted.)SYMBOLPARAMETERTEST CONDITIONSTESTCONDITIONS1LIMITSMINTYP2MAXUNITVOHHigh-level output voltageVCC = ±10%, VIL = MAX, VIH = MIN IOH = MAXVCC – 2VV= 4mA0.250.40VOLOLowLow-level output voltageleveloutputvoltageVCC = MIN, V,IL = MAX, ,IOL VIH = MINIOL = 8mA0.350.50VVIKInput clamp voltageVCC = MIN, II = IIK–0.73–1.5VI0.1mAIInput current at maximum inputDn, CPnvoltageSDn, RDnVCC = MAX, V=MAXVI = 7.0V=70V0.2mAIHighHigh–level input currentlevelinputcurrentDn, CPn20µAIHSDn, RDnVCC = MAX, V=MAXVI = 2.7V=27V40µAIDn, CPn–0.2mAILLowLow–level input currentlevelinputcurrentSDn, RDnVCC = MAX, V=MAXVI = 0.4V=04V–0.4mAIOOutput current3VCC = MAX, VO = 2.25V–30–112mAICCSupply current (total)4VCC = MAX3.04.0mANOTES:1.For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.2.All typical values are at VCC = 5V, Tamb = 25°C.3.The output conditions have been chosen to produce a current that closely approximates one half of the true short–circuit output current, I4.Measure I with the Dn, CPn, and SDn grounded, then with Dn, CPn, and RDn grounded.OS.CCAC ELECTRICAL CHARACTERISTICSLIMITSTC to +70°CSYMBOLPARAMETERTEST CONDITIONVamb = 0°CC = +5.0V ± 10%UNITCL = 50pF, RL = 500ΩMINMAXfmaxMaximum clock frequencyWaveform 180MHztPropagation delay3.014.0tPLHPHL CPn to Qn or QnWaveform 13.014.0nstPropagation delay8.0tPLHPHLSDn or RD to Qn or QnWaveform 2, 31.03.010.0nsAC SETUP REQUIREMENTSLIMITSTCSYMBOLPARAMETERTEST CONDITIONVamb = 0°C to +70°CC = +5.0V ± 10%UNITCL = 50pF, RL = 500ΩMINMAXtsu (H)Setup time, High or Low6.0tsu (L)Dn to CPnWaveform 16.0nsth (H) Hold time, High or Lowth (L)Dn to CPnWaveform 10.00.0nstw (H)CPn Pulse width tw (L)High or LowWaveform 16.06.0nstw (L)SDn or RDn Pulse width, LowWaveform 2, 36.0nstrecRecovery time, SDn or RDn to CPnWaveform 2, 36.0ns1996 Jul 014Philips SemiconductorsProduct specificationDual D-type flip-flop with set and reset74ALS74AAC WAVEFORMSFor all waveforms, VM = 1.3V.The shaded areas indicate when the input is permitted to change for predictable output performance.DnVMVMVMVMtsu(L)th(L)tsu(H)th(H)1/fmaxCPnVMVtw(L)VtMMw(H)tPLHtPHLQnVMVMtPHLtPLHQnVMVMSF00049Waveform 1.Propagation Delay for Data to Output, Data Setup and Hold Times, Clock Width, and Maximum Clock FrequencyDnSDntVMw(L)VMtRECCPnVMtPLHQnVMtPHLQnVMSC00040Waveform 2. Propagation Delay for Set to Output, Set Pulse Width and Recovery Time for Set to Clock1996 Jul 01DnRDntVMw(L)VMtRECCPnVMtPLHQnVMtPHLQnVMSC00041Waveform 3. Propagation Delay for Reset to Output, Reset Pulse Width and Recovery Time for Reset to Clock5Philips SemiconductorsProduct specificationDual D-type flip-flop with set and reset74ALS74ATEST CIRCUIT AND WAVEFORMSVCC90%tw90%AMP (V)NEGATIVEPULSEVMVMVINVOUT10%10%PULSE0.3VGENERATORD.U.T.tTHL (tff)tTLH (tr )RTCLRLtTLH (tr )tTHL (tf )90%90%AMP (V)POSITIVEPULSEVVTest Circuit for Totem-pole OutputsMM10%t10%w0.3VDEFINITIONS:Input Pulse DefinitionRL=Load resistor; see AC electrical characteristics for value.CFamilyINPUT PULSE REQUIREMENTSL=Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.AmplitudeVMRep.RatetwtTLHtTHLRT=Termination resistance should be equal to ZOUT of 74ALS3.5V1.3V1MHzpulse generators.500ns2.0ns2.0nsSC000051996 Jul 016Philips SemiconductorsProduct specification
Dual D-type flip-flop with set and reset74ALS74A
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Objective SpecificationProduct Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specificationsmay change in any manner without notice.
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Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. PhilipsSemiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or maskwork right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposesonly. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testingor modification.
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PhilipsSemiconductors1991 Jul 017Philips SemiconductorsProduct specification
Dual D-type flip-flop with set and reset74ALS74A
DIP14:plastic dual in-line package; 14 leads (300 mil)SOT27-1
1996 Jul 018
Philips SemiconductorsProduct specification
Dual D-type flip-flop with set and reset74ALS74A
SO14:plastic small outline package; 14 leads; body width 3.9 mmSOT108-1
1996 Jul 019
Philips SemiconductorsProduct specification
Dual D-type flip-flop with set and reset74ALS74A
1996 Jul 01NOTES
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