NTHD4102PT1G;NTHD4102PT3G;中文规格书,Datasheet资料

−20 V, −4.1 A, Dual P−Channel ChipFETt

Features

•Offers an Ultra Low RDS(ON) Solution in the ChipFET Package•Miniature ChipFET Package 40% Smaller Footprint than TSOP−6•Low Profile (<1.1 mm) Allows it to Fit Easily into Extremely Thin•••

Environments such as Portable Electronics

Simplifies Circuit Design since Additional Boost Circuits for GateVoltages are not Required

Operated at Standard Logic Level Gate Drive, Facilitating FutureMigration to Lower Levels using the same Basic TopologyPb−Free Package is Available

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V(BR)DSS

RDS(ON) TYP mW @ −4.5 V

−20 V

85 mW @ −2.5 V120 mW @ −1.8 V

S1S2−4.1 AID MAX

Applications

•Optimized for Battery and Load Management Applications in••

Portable Equipment such as MP3 Players, Cell Phones, and PDAsCharge Control in Battery ChargersBuck and Boost Converters

G1G2

D1P−Channel MOSFET

Value−20\"8.0−2.9−2.1−4.1

PDIDMTJ,TSTGISTL

1.12.1−16−55 to150−1.1260

A°CA°C

C7= Specific Device CodeM= Month CodeG= Pb−Free Package

WUnitVVA

Parameter

SymbolVDSSVGS

TA = 25°CTA = 85°CTA = 25°CTA = 25°C

ID

D2P−Channel MOSFETChipFET

CASE 1206ASTYLE 2

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Drain−to−Source VoltageGate−to−Source VoltageContinuous DrainCurrent (Note 1)

Steady Statet ≤10 s

Power Dissipation(Note 1)Pulsed Drain Current

Steady Statet ≤10 s

PIN

CONNECTIONS

D18D17D26D251S12G13S24G2

1234

MARKINGDIAGRAM

8765

C7 MGtp=10 ms

Operating Junction and Storage TemperatureSource Current (Body Diode)Lead Temperature for Soldering Purposes (1/8” from case for 10 s)

THERMAL RESISTANCE RATINGS

Parameter

Junction−to−Ambient, Steady State (Note 1)Junction−to−Ambient, t ≤10s (Note 1)

SymbolRqJA

Max11360

Unit°C/W

ORDERING INFORMATION

DeviceNTHD4102PT1NTHD4102PT1G

PackageChipFETChipFET(Pb−Free)

Shipping†3000/Tape & Reel3000/Tape & Reel

Stresses exceeding Maximum Ratings may damage the device. MaximumRatings are stress ratings only. Functional operation above the RecommendedOperating Conditions is not implied. Extended exposure to stresses above theRecommended Operating Conditions may affect device reliability.

1.Surface mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq[1 oz] including traces)

†For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationsBrochure, BRD8011/D.

Publication Order Number:

NTHD4102P/D

© Semiconductor Components Industries, LLC, 2011

September, 2011 − Rev. 6

1

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NTHD4102P

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic

OFF CHARACTERISTICS

Drain−to−Source Breakdown VoltageDrain−to−Source Breakdown VoltageTemperature CoefficientZero Gate Voltage Drain Current

V(Br)DSSV(Br)DSS/TJ

IDSSIGSSVGS(TH)VGS(TH)/TJRDS(ON)

VGS = −4.5 V, ID = −2.9 AVGS = −2.5 V, ID = −2.2 AVDS = −1.8 V, ID = −1.0 A

Forward Transconductance

CHARGES, CAPACITANCES, AND GATE RESISTANCEInput CapacitanceOutput Capacitance

Reverse Transfer CapacitanceTotal Gate ChargeGate−to−Source ChargeGate−to−Drain Charge

SWITCHING CHARACTERISTICS (Note 3)Turn−On Delay TimeRise Time

Turn−Off Delay TimeFall Time

DRAIN−SOURCE DIODE CHARACTERISTICSForward Diode VoltageReverse Recovery TimeCharge TimeDischarge Time

Reverse Recovery Charge

VSDtRRtatbQRR

VGS = 0 V, dIS/dt = 100 A/ms,

IS = 1.0 AVGS = 0 V, IS = −1.1 A

−0.8201550.01

mC

−1.240

Vns

td(ON)trtd(OFF)tf

VGS = −4.5 V, VDD = −16 V,ID = −2.6 A, RG = 2.0 W

5.5123223

102035

ns

CISSCOSSCRSSQG(TOT)QGSQGD

VGS = −4.5 V, VDS = −16 V,

ID = −2.6 AVGS = 0 V, f = 1.0 MHz,

VDS = −16 V

750100457.61.32.6

8.6

nCpF

gFS

VDS = −10 V, ID = −2.9 AVGS = 0 VVDS = −16 V

TJ = 25°CTJ = 85°C

VGS = 0 V, ID = −250 mA

−20

−15

−1.0−5.0\"100

nAVmV/°CmA

Symbol

Test Condition

Min

Typ

Max

Unit

Gate−to−Source Leakage CurrentON CHARACTERISTICS (Note 2)Gate Threshold Voltage

Gate Threshold Temperature CoefficientDrain−to−Source On Resistance

VDS = 0 V, VGS = \"8.0 VVGS = VDS, ID = −250 mA

−0.45

2.7851207.0

−1.5VmV/°C

80110170

mW

S

2.Pulse test: pulse width ≤ 300 ms, duty cycle ≤ 2%

3.Switching characteristics are independent of operating junction temperatures

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NTHD4102P

TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)

10−ID, DRAIN CURRENT (AMPS)987632100

1

2

3

4

5

6

−1.8 V−1.6 V−1.4 V7

8

−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

9−ID, DRAIN CURRENT (AMPS)8763210025°C125°CTJ = −55°C4VGS = −10 V to −2.8 VTJ = 25°C−2.4 V0.511.522.533.5−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics

RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)0.2

RDS(on), DRAIN−TO−SOURCERESISTANCE (NORMALIZED)0.180.160.140.120.10.080.060.040.0202

345−ID, DRAIN CURRENT (AMPS)

6

VGS = −4.5 VVGS = −2.5 V1.5

Figure 2. Transfer Characteristics

VGS = −4.5 V1.31.10.90.70.5−50−250255075100125150TJ, JUNCTION TEMPERATURE (°C)

Figure 3. On−Resistance vs. Drain Current and

Gate Voltage

10000

VGS = 0 V−IDSS, LEAKAGE (nA)10001001010.1

TJ = 125°CTJ = 100°CFigure 4. On−Resistance Variation with

Temperature

TJ = 25°C2345678−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 5. Drain−to−Source Leakage Current

vs. Voltage

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NTHD4102P

TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)

5

QT43

Q1210

Q2−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)1.2

−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)1000900C, CAPACITANCE (pF)800700600500400300200100002Crss468101214TJ = 25°CCissCoss161820ID = −2.7 ATJ = 25°C0142356Qg, TOTAL GATE CHARGE (nC)

78−VGS−VDSGATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 6. Capacitance Variation

1000

Figure 7. Gate−to−Source and Drain−to−Source

Voltage vs. Total Gate Charge

5−IS, SOURCE CURRENT (AMPS)432100.4

VGS = 0 VTJ = 25°CVDD = −10 VID = −1.0 AVGS = −4.5 Vt, TIME (ns)100

10

td(off)tftrtd(on)11

10

RG, GATE RESISTANCE (OHMS)

100

0.50.60.70.80.91.01.1

−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 8. Resistive Switching Time Variation

vs. Gate Resistance

100−ID, DRAIN CURRENT (AMPS)Figure 9. Diode Forward Voltage vs. Current

1010 ms100 ms1 ms10 ms1

0.1

VGS = −8 V SINGLE PULSETC = 25°CRDS(on) LIMITTHERMAL LIMITPACKAGE LIMITdc0.010.1110−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

100Figure 10. Maximum Rated Forward Biased

Safe Operating Area

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NTHD4102P

PACKAGE DIMENSIONS

ChipFET]CASE 1206A−03

ISSUE K

D8765NOTES:

1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.

3.MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.4.LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTALAND VERTICAL SHALL NOT EXCEED 0.08 MM.

5.DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.6.NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEADSURFACE.

DIMAbcDEee1LHEqMILLIMETERS

NOMMAX1.051.100.300.350.150.203.053.101.651.700.65 BSC0.55 BSC0.280.350.421.801.902.005°NOMMIN1.000.250.102.951.55

INCHESNOM0.0410.0120.0060.1200.0650.025 BSC0.022 BSC0.0140.0110.0710.0755°NOMMIN0.0390.0100.0040.1160.061

MAX0.0430.0140.0080.1220.0670.0170.079qL5637281HE1234E4e1ebcRESET

A0.05 (0.002)STYLE 2:PIN 1. 2. 3. 4. 5. 6. 7. 8.

SOURCE 1GATE 1SOURCE 2GATE 2DRAIN 2DRAIN 2DRAIN 1DRAIN 1

SOLDERING FOOTPRINT*12.0320.082.3620.0930.650.025PITCH8X8X0.4570.0180.660.026Basic

mmǓǒinches*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

ChipFET is a trademark of Vishay Siliconix.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:N. American Technical Support: 800−282−9855 Toll FreeLiterature Distribution Center for ON SemiconductorUSA/CanadaP.O. Box 61312, Phoenix, Arizona 85082−1312 USAPhone: 480−829−7710 or 800−344−3860 Toll Free USA/CanadaJapan: ON Semiconductor, Japan Customer Focus Center2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051Fax: 480−829−7709 or 800−344−3867 Toll Free USA/CanadaPhone: 81−3−5773−3850Email: orderlit@onsemi.comON Semiconductor Website: http://onsemi.comOrder Literature: http://www.onsemi.com/litorderFor additional information, please contact yourlocal Sales Representative.http://onsemi.com5NTHD4102P/Dhttp://oneic.com/

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