英文翻译—周建青

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毕业设计（论文）外文参考

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译文题目： Five serial configuration devices

Of Altera Data Sheet 学生姓名：周建青学号： 0709110119 专业：电子信息工程所在学院：信息技术学院指导教师：职称：

2010年 12 月 15日

说明：

要求学生结合毕业设计（论文）课题参阅一篇以上的外文资料，并翻译至少一万印刷符（或译出3千汉字）以上的译文。译文原则上要求打印（如手写，一律用400字方格稿纸书写），连同学校提供的统一封面及英文原文装订，于毕业设计（论文）工作开始后2周内完成，作为成绩考核的一部分。

Five Serial Configuration Devices of Altera Data Sheet

——From www.altera.com

Introduction

The serial configuration devices provide the following features:

■ 1-, 4-, 16-, -, and 128-Mbit flash memory devices that serially configure Stratix® III, Stratix II GX, and Stratix II FPGAs, Arria™ GX FPGAs, and the Cyclone® series FPGAs using the active serial (AS) configuration scheme ■ Easy-to-use four-pin interface

■ Low cost, low-pin count, and non-volatile memory

■ Low current during configuration and near-zero standby mode current ■ 2.7-V to 3.6-V operation

■ EPCS1 and EPCS4 available in 8-pin small outline integrated circuit (SOIC) package. EPCS16 and EPCS128 available in 8-pin or 16-pin small outline integrated circuit (SOIC) packages

■ Enables the Nios® processor to access unused flash memory through AS memory interface

■ Re-programmable memory with more than 100,000 erase/program cycles ■ Write protection support for memory sectors using status register bits ■ In-system programming support with SRunner software driver

■ In-system programming support with USB Blaster™, Ethernet Blaster™, or ByteBlaster™ II download cables

■ Additional programming support with the Altera® Programming Unit (APU) and programming hardware from BP Microsystems, System General, and other vendors

■ Software design support with the Altera Quartus® II development system for Windows-based PCs as well as Sun SPARC station and HP 9000 Series 700/800 ■ Delivered with the memory array erased (all the bits set to 1)

The term ―serial configuration devices‖ used in this document refers to Altera EPCS1, EPCS4, EPCS16, EPCS, and EPCS128. Functional Description

With SRAM-based devices that support active serial configuration, configuration data must be reloaded each time the device powers up, the system reconfigures, or when new configuration data is required. Serial configuration devices are flash memory devices with a serial interface that can store configuration data for FPGA devices that

support active serial configuration and reload the data to the device upon power-up or reconfiguration. Table 4–1 lists the serial configuration devices.

Table 4–1. Serial Configuration Devices (3.3-V Operation) Device Memory Size (Bits) EPCS1 1,048,57EPCS4 4,194,30EPCS16 16,777,21EPCS 67,108,86EPCS128 134,217,72For an 8-pin SOIC package, you can migrate vertically from the EPCS1 to the EPCS4 or EPCS16 since the EPCS devices are offered in the same device package. Similarly, for a 16-pin SOIC package, you can migrate vertically from the EPCS16 to the EPCS or EPCS128.

EPCS16 is available in 8-pin and 16-pin SOIC packages.

Table 4–2 lists the serial configuration device used with each Stratix IV FPGA and the configuration file size. For lager Stratix IV devices such as EPC4SGX290 and EP4SGX360.

Table 4–2. Serial Configuration Device Support for Stratix IV Devices Raw Binary File Serial Configuration Device Stratix IV evice Size (Mbits) EPCS1 EPCS4 EPCS16 EPCS EPCS128 (1) EP4SE110 53 — — — v v EP4SE230 104 — — — — v EP4SE290 141 — — — — v (2) EP4SE360 141 — — — — v (2) EP4SE530 188 — — — — — EP4SE680 234 — — — — — EP4SGX70 53 — — — v v EP4SGX110 53 — — — v v EP4SGX230 104 — — — — v EP4SGX290 141 — — — — v (2) EP4SGX360 141 — — — — v (2) EP4SGX530 188 — — — — — Notes to Table 4–2: (1) These values are preliminary. These are ncompressed file sizes. (2) This is with the Stratix IV compression feature enabled.

Table 4–3 lists the serial configuration device used with each Stratix III FPGA and the configuration file size. Stratix III devices can be used with EPCS16, EPCS, or EPCS128.

Table 4–3. Serial Configuration Device Support for Stratix III Devices Stratix III Raw Binary File Serial Configuration Device evice Size (Bits) (1) EPCS1 EPCS4 EPCS16 EPCS EPCS128 EP3SL50 22,178,792 — — v (2) v v EP3SL70 22,178,792 — — v (2) v v EP3SL110 47,413,312 — — — v v EP3SL150 47,413,312 — — — v v EP3SL200 93,324,656 — — — v (2) v EP3SL340 117,384,6 — — — — v EP3SE50 25,1,968 — — — v v EP3SE80 48,225,392 — — — v v EP3SE110 48,225,392 — — — v v EP3SE260 93,324,656 — — — v (2) v Notes to Table 4–3: (1) These are uncompressed file sizes.

(2) This is with the Stratix III compression feature enabled.

Table 4–4 lists the serial configuration device used with each Stratix II GX FPGA and the configuration file size. Stratix II GX devices can be used with EPCS16, EPCS, or EPCS128.

Table 4–4. Serial Configuration Device Support for Stratix II GX Devices Stratix II GX Raw Binary Serial Configuration Device Device FileSize (Bits) EPCS1 EPCS4 EPCS16 EPCS EPCS128 (1) EP2SGX30C 9,0,672 — — v v v EP2SGX30D EP2SGX60C EP2SGX60D EP2SGX60E 16,951,824 — — v (2) v v EP2SGX90E 25,699,104 — — — v v EP2SGX90F EP2SGX130G 37,325,760 — — — v v Notes to Table 4–4: (1) These are uncompressed file sizes.

(2) This is with the Stratix II GX compression feature enabled.

Table 4–5 lists the serial configuration device used with each Stratix II FPGA and the configuration file size. Stratix II devices can be used with EPCS4, EPCS16, EPCS, or EPCS128.

Table 4–5. Serial Configuration Device Support for Stratix II Devices RawBinary Serial Configuration Device Stratix II Device File Size(Bits) EPCS4 EPCS16 EPCS EPCS128 EP2S15 4,721,4 v (2) v v v EP2S30 9,0,672 — v v v EP2S60 16,951,824 — v (2) v v EP2S90 25,699,104 — v (2) v v EP2S130 37,325,760 — — v v EP2S180 49,814,760 — — v v Notes to Table 4–5: (1) These are uncompressed file sizes.

(2) This is with the Stratix II compression feature enabled.

Table 4–6 lists the serial configuration device used with each Arria GX FPGA and the configuration file size. Arria GX devices can be used with EPCS16, EPCS, or EPCS128.

Table 4–6. Serial Configuration Device Support for Arria GX Devices Serial Configuration Device Arria GX Raw Binary EPCS1 EPCS4 EPCS16 EPCS EPCS128 Device FileSize EP1AGX20C 9,0,672 — — v v v EP1AGX35C 9,0,672 — — v v v EP1AGX35D EP1AGX50C EP1AGX50D 16,951,824 — — v (2) v v EP1AGX60C — — v (2) v v EP1AGX60D 16,951,824 EP1AGX60E EP1AGX90E 25,699,104 — — — v v Notes to Table 4–6: (1) These are uncompressed file sizes.

(2) This is with the Arria GX compression feature enabled.

Table 4–7 lists the serial configuration device used with each Cyclone III FPGA and the configuration file size. Cyclone III devices can be used with EPCS4, EPCS16, EPCS, or EPCS128.

Table 4–7. Serial Configuration Device Support for Cyclone III Devices Cyclone III Raw Binary File Serial Configuration Device Device Size (Bits) (1) EPCS1 EPCS4 EPCS16 EPCS EPCS128 EP3C5 2,944,088 — v v v v EP3C10 2,944,088 — v v v v EP3C16 4,086,848 — v v v v EP3C25 5,748,552 — v (2) v v v EP3C40 9,534,304 — — v v v EP3C55 14,8,560 — — v v v EP3C80 19,965,752 — — v (2) v v EP3C120 28,571,696 — — — v v Notes to Table 4–7: (1) These are uncompressed file sizes.

(2) This is with the Cyclone III compression feature enabled.

Table 4–8 lists the serial configuration device used with each Cyclone II FPGA and the configuration file size. Cyclone II devices can be used with EPCS1, EPCS4, EPCS16, EPCS, or EPCS128.

Table 4–8. Serial Configuration Device Support for Cyclone II Devices Cyclone II Raw Binary File Serial Configuration Device Device Size (Bits) (1) EPCS1 EPCS4 EPCS16 EPCS EPCS128 EP2C5 1,265,792 v (2) v v v v EP2C8 1,983,536 — v v v v EP2C20 3,2,496 — v v v v EP2C35 6,848,608 — — v v v EP2C50 9,951,104 — — v v v EP2C70 14,319,216 — — v v v Notes to Table 4–8: (1) These are uncompressed file sizes.

(2) This is with the Cyclone II compression feature enabled.

Table 4–9 lists the serial configuration device used with each Cyclone FPGA and the configuration file size. Cyclone devices can be used with EPCS1, EPCS4, EPCS16, EPCS, or EPCS128.

Table 4–9. Serial Configuration Device Support for Cyclone Devices Raw Binary File Serial Configuration Device Cyclone Device Size (Bits) (1) EPCS1 EPCS4 EPCS16 EPCS EPCS128 EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 627,376 924,512 1,167,216 2,323,240 3,559,608 v v v (2) — — 5

v v v v v v v v v v v v v v v v v v v v Notes to Table 4–9:

(1) These are uncompressed file sizes.

(2) This is with the Cyclone compression feature enabled.

With the new data-decompression feature in the Stratix III, Stratix II GX, and Stratix II FPGAs, Arria GX FPGAs, and Cyclone FPGA families, you can use smaller serial configuration devices to configure larger FPGAs. F For more information about the FPGA decompression feature, refer to the configuration chapter in the appropriate device handbook.

The serial configuration devices are designed to configure Stratix III, Stratix II GX, and Stratix II FPGAs and the Cyclone series FPGAs and cannot configure other existing Altera FPGA device families.

Accessing Memory in Serial Configuration Devices

You can access the unused memory locations of the serial configuration device to store or retrieve data through the Nios processor and SOPC Builder. SOPC Builder is an Altera tool for creating bus-based (especially microprocessor-based) systems in Altera devices. SOPC Builder assembles library components such as processors and memories into custom microprocessor systems.

SOPC Builder includes the EPCS device controller core, which is an interface core specifically designed to work with the serial configuration device. With this core, you can create a system with a Nios embedded processor that allows software access to any memory location within the serial configuration device. F For more information about accessing memory within the serial configuration device, refer to the Active Serial Memory Interface Data Sheet. Active Serial FPGA Configuration

The following Altera FPGAs support Active Serial (AS) configuration scheme with serial configuration devices: ■ Stratix IV ■ Stratix III ■ Stratix II GX ■ Stratix II ■ Arria GX

■ Cyclone series FPGAs

This section is only relevant for FPGAs that support the AS configuration scheme. There are four signals on the serial configuration device that interface directly with the FPGA’s control signals. The serial configuration device signals DATA, DCLK, ASDI, and nCS interface with DATA0, DCLK, ASDO, and nCSO control signals on the FPGA, respectively. Figure 4–2 shows a serial configuration device

programmed via a download cable, which configures an FPGA in AS mode. Figure

4–3 shows a serial configuration device programmed using the APU or a third-party programmer configuring an FPGA in AS configuration mode.

Figure 4–2. Cyclone FPGA Configuration in AS Mode (Serial Configuration Device Programmed Using Download Cable)

Notes to Figure 4–2: (1) VCC = 3.3 V.

(4) For more information about configuration pin I/O requirements in an AS scheme for a Cyclone III FPGA, refer to the Configuring Cyclone III Devices chapter in volume 1 of the Cyclone III Device Handbook.

Figure 4–3. Cyclone FPGA Configuration in AS Mode (Serial Configuration Device Programmed by APU or Third-PartyProgrammer)

Notes to Figure 4–3: (1) VCC = 3.3 V.

(4) For more information about configuration pin I/O requirements in an AS scheme for a Cyclone III FPGA, refer to the Configuration Cyclone III Devices chapter in volume 1 of the Cyclone III Device Handbook.

The FPGA acts as the configuration master in the configuration flow and provides the clock to the serial configuration device. The FPGA enables the serial configuration device by pulling the nCS signal low via the nCSO signal (refer to Figure 4–2 and Figure 4–3). Subsequently, the FPGA sends the instructions and addresses to the serial configuration device via the ASDO signal. The serial configuration device responds to the instructions by sending the configuration data to the FPGA’s DATA0 pin on the falling edge of DCLK. The data is latched into the FPGA on the next DCLK signal’s falling edge.

Before the FPGA enters configuration mode, ensure that VCC of the EPCS is ready. If it is not, you need to hold nCONFIG low until all power rails of EPCS are ready. F Refer to the configuration chapter in the appropriate device handbook for more information about configuring the FPGAs in AS mode or other configuration modes.

Multiple devices can be configured by a single EPCS device. However, serial configuration devices cannot be cascaded. Refer to Table 4–1 to ensure the

programming file size of the cascaded FPGAs does not exceed the capacity of a serial configuration device. Figure 4–4 shows the AS configuration scheme with multiple FPGAs in the chain. The first FPGA is the configuration master and has its MSEL[] pins set to AS mode. The following FPGAs are configuration slave devices and have their MSEL[] pins set to PS mode.

Figure 4–4. Multiple Devices in AS Mode

Notes to Figure 4–4: (1) VCC = 3.3 V.

(2) Serial configuration devices cannot be cascaded. (3) Connect the FPGA MSEL[] input pins to select the AS configuration mode. For details, refer to the appropriate FPGA family chapter in the Configuration Handbook. (4) Connect the FPGA MSEL[] input pins to select the PS configuration mode. For details, refer to the appropriate FPGA family chapter in the Configuration Handbook.

(5) For more information about configuration pin I/O requirements in an AS scheme for a Cyclone III FPGA, refer to the Configuring Cyclone III Devices chapter in volume 1 of the Cyclone III Device Handbook.

五种Altera公司串行配置设备的数据表单

——摘自www.altera.com

介绍

该串行配置设备具有以下功能：

■通过1 - ，4 - ，16 - ， -和128兆位闪存设备，使用主动串行（AS）的配置方案串行配置Stratix®III, Stratix II GX、Stratix II FPGAs、Arria™ GX和Cyclone® 系列的可编程逻辑控件 ■简单易用的四针接口 ■低成本，低引脚数的永久内存 ■低电流配置，待机模式近乎零电流 ■工作电压区间为2.7 - V至3.6 V

■EPCS1和EPCS4 具有8引脚小型集成电路（SOIC）封装，EPCS16和EPCS128提供8引脚或16引脚小型集成电路（SOIC）封装

■允许使用Nios ®处理器通过主动串行（AS）内存界面存取未使用的闪存记忆体 ■可编程存储器寿命在10万次擦写以上 ■通过状态寄存器开关提供内存写保护支持 ■通过SRunner软件驱动提供系统内编程支持

■通过USB Blaster™、Ethernet Blaster™、或ByteBlaster™ II下载电缆提供系统内编程支持

■通过Altera ®的编程单元（APU）、BP Microsystems、System General及其他品牌的硬件提供附加编程支持

■通过为基于Windows平台PC的Altera Quartus® II开发系统、 Sun SPARC 工作站以及HP 9000系列的700/800系统提供软件设计支持 ■内存阵列在传输后实现清除（全部位设置为1）

―串行配置设备‖在本文档中指的是Altera型号为EPCS1、EPCS4、EPCS16、EPCS和EPCS128设备。

译者：刘千

功能描述

作为基于SRAM的支持主动串行配置的设备，配置数据必须在设备每次开启、重新配置或需要添加新配置数据时重新载入。串行配置设备是具有串行接口的闪存设备，可以为支持主动串行配置的可编程逻辑器件储存配置数据，并在设备开启或重新配置时重新加载数据。表4-1列出了这些串行配置设备名单。

表4-1 串行配置设备（工作电压3.3V）

设备 EPCS1 EPCS4 EPCS16 EPCS EPCS128 存储容量（位） 1,048,574,194,3016,777,2167,108,86134,217,72由于EPCS设备是以相同的设备封装提供的，对于8引脚的小型集成电路（SOIC）封装，您可以从EPCS1设备垂直转向EPCS4或EPCS16设备。同样，对于16引脚的小型集成电路（SOIC）封装，您可以从EPCS16设备垂直转向EPCS或EPCS128设备。

EPCS16同时具有8引脚和16引脚小型集成电路SOIC封装。

表4-2列出了与Stratix 四代现场可编程门阵列配合使用的各种串行配置器件及其配置文件的大小。相对应的大型Stratix四代设备包括EPC4SGX290和设备EP4SGX360等。

表4-2 支持Stratix 四代设备的串行配置设备

Stratix 三代设备 EP4SE110 EP4SE230 EP4SE290 EP4SE360 EP4SE530 EP4SE680 EP4SGX70 EP4SGX110 EP4SGX230 EP4SGX290 EP4SGX360 EP4SGX530 原始的二进制文件大小（兆位） 53 104 141 141 188 234 53 53 104 141 141 188 串行配置设备 EPCS1 — — — — — — — — — — — — 2

EPCS4 EPCS16 EPCS EPCS128 — — — — — — — — — — — — — — — — — — — — — — — — v — — — — — v v — — — — v v v (2) v (2) — — v v v v (2) v (2) — 译者：刘千

表4-2备注：

（1）这些值均为初步值，是非压缩的文件大小。

（2）这是在Stratix 四代设备压缩功能启用情况下得出的值。

表4-3列出了与Stratix 三代现场可编程门阵列配合使用的各种串行配置器件及其配置文件的大小。Stratix 三代设备可与EPCS16、EPCS或EPCS128配合使用。

表4-3 支持Stratix 三代设备的串行配置设备

Stratix 三代设备 EP3SL50 EP3SL70 EP3SL110 EP3SL150 EP3SL200 EP3SL340 EP3SE50 EP3SE80 EP3SE110 EP3SE260 表4-3备注：

（1）这些均为非压缩的文件大小。

（2）这是在Stratix 三代压缩功能启用情况下得出的值。

表4-4列出了与Stratix二代GX现场可编程门阵列配合使用的各种串行配置器件及其配置文件的大小。Stratix二代GX设备可与EPCS16、EPCS或EPCS128配合使用。

译者：刘千

原始的二进制文件大小EPCS1 （位） 22,178,792 — 22,178,792 — 47,413,312 — 47,413,312 — 93,324,656 — 117,384,6 — 25,1,968 — 48,225,392 — 48,225,392 — 93,324,656 — 串行配置设备 EPCS4 EPCS16 EPCS EPCS128 — — — — — — — — — — v (2) v v (2) v — v — v — v (2) — — — v — v — v — v (2) v v v v v v v v v v 表4-4 支持Stratix GX 二代设备的串行配置设备 Stratix GX 二代设备 EP2SGX30C EP2SGX30D EP2SGX60C EP2SGX60D EP2SGX60E EP2SGX90E EP2SGX90F EP2SGX130G 表4-4备注：

（1）这些均为非压缩的文件大小。

（2）这是在Stratix 二代GX设备压缩功能启用情况下得出的值。

表4-5列出了与Stratix 二代现场可编程门阵列配合使用的各种串行配置器件及其配置文件的大小。Stratix 二代GX设备可与EPCS4、EPCS16、EPCS或EPC配合使用。

表4-5 支持Stratix二代设备的串行配置设备

Stratix 二代设备 EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180 表4-5备注：

（1）这些均为非压缩的文件大小。

（2）这是在Stratix 二代设备压缩功能启用情况下得出的值。

表4-6列出了与Arria GX可编程逻辑器件配合使用的各种串行配置器件及其配置文件的大小。Arria GX设备可与EPCS16、EPCS、EPCS或EPCS128配合使用。

译者：刘千

原始的二进制文件大小 EPCS1 （位） 9,0,672 16,951,824 25,699,104 37,325,760 — — 串行配置设备 EPCS4 EPCS16 EPCS EPCS128 — — v v (2) v v v v — — — — — — v v v v 原始的二进制串行配置设备文件大小 EPCS4 EPCS16 EPCS EPCS128 （位） 4,721,4 9,0,672 16,951,824 25,699,104 37,325,760 49,814,760 v (2) v — v — v (2) — v (2) — — — — v v v v v v v v v v v v 表4-6 支持Arria GX 设备的串行配置设备

原始的二进Arria GX 设备制文件大小（位） EP1AGX20C 9,0,672 EP1AGX35C 9,0,672 EP1AGX35D EP1AGX50C EP1AGX50D EP1AGX60C EP1AGX60D EP1AGX60E EP1AGX90E 表4-6备注：

（1）这些均为非压缩的文件大小。

（2）这是在Arria GX设备压缩功能启用情况下得出的值。

表4-7列出了与Cyclone三代现场可编程门阵列配合使用的各种串行配置器件及其配置文件的大小。Cyclone三代设备可与EPCS4、EPCS16、EPCS、EPCS或EPCS128配合使用。

表4-7 支持Cyclone三代设备的串行配置设备 Cyclone 原始的二进串行配置设备三代设备制文件大小 EPCS1 EPCS4 EPCS16 EPCS EPCS128 （位） EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120 表4-7备注：

（1）这些均为非压缩的文件大小。

（2）这是在Cyclone三代设备压缩功能启用情况下得出的值。

表4-8列出了与Cyclone二代现场可编程门阵列配合使用的各种串行配置器件及

译者：刘千

串行配置设备 EPCS1 — — — — EPCS4 — — — — EPCS16 EPCS EPCS128 v v v (2) v (2) v v v v v v v v 16,951,824 16,951,824 25,699,104 — — — v v 2,944,088 2,944,088 4,086,848 5,748,552 9,534,304 14,8,560 19,965,752 28,571,696 — — — — — — — — v v v v v v v (2) v — v — v — v (2) — — v v v v v v v v v v v v v v v v 其配置文件的大小。Cyclone二代设备可与EPCS1、EPCS4、EPCS16、EPCS、EPCS或EPCS128配合使用。

表4-8 支持Cyclone二代设备的串行配置设备 Cyclone 原始的二进串行配置设备二代设备制文件大小 EPCS1 EPCS4 EPCS16 EPCS EPCS128 （位） EP2C5 1,265,792 v (2) v v v v EP2C8 1,983,536 — v v v v EP2C20 3,2,496 — v v v v EP2C35 6,848,608 — — v v v EP2C50 9,951,104 — — v v v EP2C70 14,319,216 — — v v v 表4-8备注：

（1）这些均为非压缩的文件大小。

（2）这是在Cyclone二代设备压缩功能启用情况下得出的值。

表4-9列出了与Cyclone现场可编程门阵列配合使用的各种串行配置器件及其配置文件的大小。Cyclone设备可与EPCS1、EPCS4、EPCS16、EPCS、EPCS或EPCS128配合使用。

表4-9 支持Cyclone设备的串行配置设备原始的二进串行配置设备 Cyclone 设备制文件大小 EPCS1 EPCS4 EPCS16 EPCS EPCS128 （位） EP1C3 627,376 v v v v v EP1C4 924,512 v v v v v EP1C6 1,167,216 v (2) v v v v EP1C12 2,323,240 — v v v v EP1C20 3,559,608 — v v v v 表4-9备注：

（1）这些均为非压缩的文件大小。

（2）这是在Cyclone设备压缩功能启用情况下得出的值。

随着Stratix 三代、 Stratix 二代 GX、 Stratix 二代、Arria GX和Cyclone系列可编程逻辑器件引入新式解压缩功能，您可以用较小的串行配置设备来配置较大的可编程逻辑器件。

注：如需有关可编程逻辑器件的解压缩功能的详细信息，请参阅相应设备手册中的配置章节。

译者：刘千

这类串行配置器件系为配置Stratix 三代、 Stratix 二代 GX、 Stratix 二代以及Cyclone系列可编程逻辑器件设计，不得用于配置其他现有的Altera可编程逻辑器件。

在串行配置设备中读取内存

您可以访问串行配置设备未使用的内存存储位置，通过Nios处理器和SOPC Builder编码程序储存或检索数据。SOPC Builder编码程序是一种用于创建基于总线（尤其是微处理器为基础的）系统的Altera工具，它能够将诸如处理器和内存的库组件组合定制成微处理器系统。

SOPC Builder编码程序包括EPCS设备控制器的核心。该核心是专门设计用来与串行配置设备工作的接口。有了这个核心，您就可以创建一个带有嵌入式Nios处理器的系统，并允许软件访问串行配置设备中的任何内存位置。注：更多有关在串行配置设备中访问内存的信息，请参阅主动串行内存接口的数据资料页。

主动串行可编程逻辑器件配置

下列是Altera公司现场可编程门阵列通过串行配置设备支持主动串行（AS）配置方案 ■Stratix四代 ■Stratix三代 ■Stratix 二代 GX ■Stratix二代 ■Arria GX

■Cyclone系列现场可编程门阵列

本节只与支持主动串行配置方案的可编程逻辑器件相关。

串行配置设备有4种信号与可编程逻辑器件的控制信号直接交互，其DATA、DCLK、ASDI、和nCS信号分别与可编程逻辑器件的控制信号DATA0、DCLK、ASDO和nCSO交互。图4-2显示了一个通过下载电缆编程的串行设备

7 译者：刘千

在AS模式下配置可编程逻辑器件的样例。图4-3显示了一个使用APU或第三方程序控制器编程的串行设备在AS模式下配置可编程逻辑器件的样例。图4-2是AS模式下的Cyclone可编程逻辑器件配置样例（使用下载电缆对串行配置设备编程）

图4-2说明：（1）Vcc= 3.3V

（2）串行配置设备不得级联。

（3）连接可编程逻辑器件MSEL[]的输入引脚以选择AS配置模式。有关详细信息，请参阅配置手册中相应的可编程逻辑器件产品章节。

（4）更多关于Cyclone三代可编程逻辑器件在AS方案中的配置引脚I/O需求，请参阅《Cyclone三代设备手册》第一卷中《配置Cyclone三代设备》有关章节。

译者：刘千

图4-3是AS模式下的Cyclone可编程逻辑器件配置样例（使用APU或第三方程序控制器编程的串行配置设备）

图4-3说明：（1）Vcc= 3.3V

（2）串行配置设备不得级联。

（3）连接可编程逻辑器件MSEL[]的输入引脚以选择AS配置模式。有关详细信息，请参阅配置手册中相应的可编程逻辑器件产品章节。

（4）更多关于Cyclone三代可编程逻辑器件在AS方案中的配置引脚I/O需求，请参阅《Cyclone三代设备手册》第一卷中《配置Cyclone三代设备》有关章节。

可编程逻辑器件在配置流程中起主配置作用，并向串行配置设备提供时间基准。可编程逻辑器件通过nCSO信号将nCS信号拉低，从而启动串行配置设备（参见图4-2和图4-3）。随后，该可编程逻辑器件通过ASDO信号向串行配置设备发送指令和地址。后者通过向可编程逻辑器件DCLK下降沿的DATA0 引脚发送配置数据的方式响应。这些数据在下一次DCLK信号下降沿中被锁存进可编程逻辑器件。

注：在可编程逻辑器件进入配置模式前，请确认EPCS的VCC已经准备就绪。否则，您需要将nCONFIG保持在低水平直至EPCS的所有电源导轨准备就绪。可编程逻辑器件在AS配置模式中控制nSTATUS和CONF_DONE引脚。如果

CONF_DONE信号未在配置结束时升高，或者信号过早升高，可编程逻辑器件将把nSTATUS引脚调低以重新启动配置。在成功配置后，可编程逻辑器件释放

9 译者：刘千

CONF_DONE引脚，允许外部10kΩ电阻将该信号拉高。CONF_DONE信号升高后，初始化工作即开始。初始化后，可编程逻辑器件进入用户模式。

注：有关更多在AS或其他配置模式中配置可编程逻辑器件的信息，请参阅相关设备手册中的配置章节。

多个设备可以通过单个EPCS设备进行配置。不过，串行配置设备不能级联。请参考表4-1以确保级联可编程逻辑器件的编程文件体积小于串行配置设备的容量。图4-4显示了对多个链接的可编程逻辑器件的AS配置方案。第一个可编程逻辑器件是主配置，其MSEL[]引脚被设为AS模式。其他器件是从配置设备，其MSEL[]均被设为PS模式。图4-4 AS模式用于多个设备

图4-4说明：（1）Vcc= 3.3V

（2）串行配置设备不得级联。

（3）连接可编程逻辑器件MSEL[]的输入引脚以选择AS配置模式。有关详细信息，请参阅配置手册中相应的可编程逻辑器件产品章节。

（4）连接可编程逻辑器件MSEL[]的输入引脚以选择PS配置模式。更多细节请参阅配置手册中相应的可编程逻辑器件产品章节。

（5）关于Cyclone三代可编程逻辑器件在AS方案中的配置引脚I/O需求，请参阅《Cyclone三代设备手册》第一卷中《配置Cyclone三代设备》有关章节。

译者：刘千

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