EL7532

EL7532

Monolithic 2A Step-Down Regulator

The EL7532 is a synchronous, integrated FET 2A step-down regulator with internal compensation. It operates with an input voltage range from 2.5V to 5.5V, which accommodates supplies of 3.3V, 5V, or a single Li-Ion battery source. The output can be externally set from 0.8V to VIN with a resistive divider.

The EL7532 features PWM mode control. The operating frequency is typically 1.5MHz. Additional features include a 100ms Power-On-Reset output, <1µA shut-down current, short-circuit protection, and over-temperature protection.The EL7532 is available in the 10-pin MSOP package, making the entire converter occupy less than 0.18 in2 of PCB area with components on one side only. The package is specified for operation over the full -40°C to +85°C temperature range.

Features

•2A continuous current (from -40°C to +85°C)

•Less than 0.18 in2 footprint for the complete 2A converter•Max height 1.1mm MSOP10•1.5MHz (typ.) switching frequency•100ms Power-On-Reset output (POR)

•Internally-compensated voltage mode controller•Up to 94% efficiency•<1µA shut-down current

•Overcurrent and over temperature protection•Pb-Free plus anneal available (RoHS compliant)

Applications

•PDA and pocket PC computers•Bar code readers

Ordering Information

PART NUMBER

(BRAND)EL7532IY(BABAA)EL7532IY-T7(BABAA)EL7532IY-T13(BABAA)EL7532IYZ

(BAARA) (Note)EL7532IYZ-T7(BAARA) (Note)EL7532IYZ-T13(BAARA) (Note)

PACKAGE10-Pin MSOP10-Pin MSOP10-Pin MSOP10-Pin MSOP (Pb-free)10-Pin MSOP (Pb-free)10-Pin MSOP (Pb-free)

TAPE &REEL

-7”13”-7”13”

PKG.DWG. #MDP0043MDP0043MDP0043MDP0043MDP0043MDP0043

•ADSL Modems•Portable instruments

•Li-Ion battery powered devices•ASIC/FPGA/DSP supplies•Set Top Boxes

Typical Application Schematic

VIN (2.5V-6V)

C110µF

R3100ΩC30.1µF

VINVDD

VOLX

L11.8µH

VO (1.8V@ 2A)

NOTE:Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

EL7532

ENPORRSI

FBSGNDPGND

C210µFR2*124kΩ

R1*100kΩ

* VO = 0.8V * (1 + R2 / R1)

Pinout

1SGND2PGND3LX4VIN5VDD

FB10VO9POR8EN7RSI6

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.1-888-INTERSIL or 1-888-468-3774|Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2004, 2005. All Rights Reserved.

All other trademarks mentioned are the property of their respective owners.

EL7532

Absolute Maximum Ratings (TA = 25°C)

VIN, VDD, POR to SGND. . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5VLX to PGND. . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V)RSI, EN, VO, FB to SGND. . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V)PGND to SGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3VPeak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4AESD Classification

Human Body Model (Per JESD22-A114-B) . . . . . . . . . . . .Class 2

Thermal Information

Thermal Resistance (Typical)

θJA (°C/W)

MSOP10 Package (Note 1) . . . . . . . . . . . . . . . . . . . 115Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°CStorage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°CJunction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of thedevice at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE:All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA

NOTE:

1.θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379.

Electrical Specifications

PARAMETER

DC CHARACTERISTICSVFBIFBVIN, VDDVIN,OFFVIN,ONIDD

VDD = VIN = VEN = 3.3V, C1 = C2 = 10µF, L = 1.8µH, VO = 1.8V, unless otherwise specified.

CONDITIONS

MIN

TYP

MAX

UNIT

DESCRIPTION

Feedback Input VoltageFeedback Input CurrentInput Voltage

Minimum Voltage for ShutdownMaximum Voltage for StartupSupply Current

VIN fallingVIN rising

PWM, VIN = VDD = 5VEN = 0, VIN = VDD = 5V

790800810250

mVnAVVVµAµAmΩmΩA°C°C

2.522.2

4000.152353

T risingT falling

VEN, VRSI = 0V and 3.3VVDD = 3.3VVDD = 3.3VVFB risingVFB fallingISINK = 5mA

VIN = 2.5V to 6V, IOUT = 2A, VOUT = 1.8VVIN = 3.3V, VOUT = 1.8V, IOUT = 0 to 2A

86

350.10.5

0.8-1

145130

5.52.22.450018065

RDS(ON)-PMOS

PMOS FET Resistance

VDD = 5V, wafer test onlyVDD = 5V, wafer test only

RDS(ON)-NMOSNMOS FET ResistanceILMAXTOT,OFFTOT,ONIEN, IRSIVEN1, VRSI1VEN2, VRSI2VPOR

Current Limit (GBD)

Over-temperature Threshold (GBD)Over-temperature Hysteresis (GBD)EN, RSI Current

EN, RSI Rising ThresholdEN, RSI Falling Threshold

Minimum VFB for POR, WRT Targeted VFB ValuePOR Voltage DropLine Regulation (GBD)Load Regulation (GBD)

12.4

VVV

95%%

VOLPORVLINEREGVLOADREG

70mV%/V%

AC CHARACTERISTICSFPWMtRSItSStPOR

PWM Switching FrequencyMinimum RSI Pulse Width (GBD)Soft-start Time (GBD)

Power On Reset Delay Time (GBD)

80

Guaranteed by design

1.35

1.525650100

1201.6550

MHznsµsms

GBD = Guaranteed By Design

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Pin Descriptions

PIN NUMBER

12345678910

PIN NAMESGNDPGNDLXVINVDDRSIENPORVOFB

Negative supply for the controller stageNegative supply for the power stage

Inductor drive pin; high current digital output with average voltage equal to the regulator output voltagePositive supply for the power stagePower supply for the controller stage

Resets POR timer; Connect to ground if not usedEnable; Can be connected directly to the VIN for enablePower on reset open drain output; Leave open if not usedOutput voltage sense pin

Voltage feedback input; connected to an external resistor divider between VO and SGND for variable output

PIN FUNCTION

Block Diagram

59

VDDVO

10pF

+-CURRENT LIMIT

+-PWM COMPARATOR

CONTROL LOGIC

124K

VIN

4

10

FB5M-+PWM COMPEN-SATION

100K

CLOCK1.5MHz

EN

RAMPGENERATOR

P-DRIVER

LX

1.8µ

3

7

1.8V2A

EN

SOFT-START

N-DRIVER

UNDER-VOLTAGE LOCKOUT

TEMPERATURE SENSE

10µF10µF

2.5V-5V

+–BANDGAP REFERENCE

PGNDPOR

2

100KPG

1

SGND

POR

8

6RSI

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Typical Performance Curves

10080EFFICIENCY (%)6040VO=1.8V2000

MAXIMUM EFFICIENCY, η=95%0.5

1

1.5

IOUT (A)

2

2.5

EFFICIENCY (%)1008060VO=1.8V402000

MAXIMUM EFFICIENCY, η=95%0.5

1

1.5

IOUT (A)

2

2.5

VO=2.5VVO=1.2VVO=1.2VVO=3.3VFIGURE 1.EFFICIENCY vs IOUT @ VIN=5VFIGURE 2.EFFICIENCY vs IOUT @ VIN=3.3V

1008060VO=1.8V4020MAXIMUM EFFICIENCY, η=94%00

0.5

1

1.5

IOUT (A)

2

2.5

VO=1.2VVO CHANGES (%)EFFICIENCY (%)10.60.2-0.2-0.6-12.5

VO=2.5VVO=3.3VVO=0.8VIO=2A33.544.555.56

VIN (V)

FIGURE 3.EFFICIENCY vs IOUT @ VIN=2.5V

FIGURE 4.LINE REGULATION

10.6

VO CHANGES (%)0.2-0.2-0.6-10

0.5

1

1.5

IOUT (A)

2

2.5

VO=0.8VVO=3.3V

VO CHANGES (%)10.60.2-0.2-0.6-1

VO=0.8VVO=2.5V

00.511.5

IOUT (A)

22.5

FIGURE 5.LOAD REGULATION @ VIN=5VFIGURE 6.LOAD REGULATION @ VIN=3.3V

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Typical Performance Curves (Continued)

1

∆VIN

VO CHANGES (%)0.5

VO=0.8V

iL

0

VO=1.8V

-0.5

∆VO

0

0.5

1

1.5

IOUT (A)

2

2.5

1µs/d

10mV/d

VLX

2V/d0.5A/d100mV/d

-1

FIGURE 7.LOAD REGULATION @ VIN=2.5VFIGURE 8.LOAD REGULATION @ VIN=2.5V

VIN(1V/d)VIN(2V/d)

IIN

(0.5A/d)

VO(2V/d)POR(2V/d)

VO(1V/d)

0.5ms/d

50ms/d

FIGURE 9.START-UP 1FIGURE 10.START-UP 2

VIN(2V/d)

∆VO

VO(2V/d)

50mV/d

RSI(2V/d)POR(2V/d)

2A

IO

0.1A

50ms/d0.5ms/d

FIGURE 11.POR FUNCTIONFIGURE 12.TRANSIENT RESPONSE

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Typical Performance Curves (Continued)

0.6POWER DISSIPATION (W)0.50.4

JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD486mW

10.9POWER DISSIPATION (W)0.80.70.60.50.40.30.20.10

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD870mW

MSOP8/11105°C/WθM0.30.20.10

JA=P8/12006°C/WSOθJA=025507585100125025507585100125

AMBIENT TEMPERATURE (°C)AMBIENT TEMPERATURE (°C)

FIGURE 13.PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATUREFIGURE 14.PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

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Applications Information

Product Description

The EL7532 is a synchronous, integrated FET 2A step-down regulator which operates from an input of 2.5V to 6V. The output voltage is user-adjustable with a pair of external resistors.

The internally-compensated controller makes it possible to use only two ceramic capacitors and one inductor to form a complete, very small footprint 2A DC-DC converter.

Where RL is the DC resistance on the inductor and RDSON1 the PFET on-resistance, nominal 70mΩ at room temperature with tempco of 0.2mΩ/°C.

As the input voltage drops gradually close or even below the preset VO, the converter gets into 100% duty ratio. At this condition, the upper PFET needs some minimum turn-off time if it is turned off. This off-time is related to input/output conditions. This makes the duty ratio appear randomly and increases the output ripple somewhat until the 100% duty ratio is reached. A larger output capacitor could reduce the random-looking ripple. Users need to verify if this condition has an adverse effect on the overall circuit if close to 100% duty ratio is expected.

Start-Up and Shut-Down

When the EN pin is tied to VIN, and VIN reaches

approximately 2.4V, the regulator begins to switch. The output voltage is gradually increased to ensure proper soft-start operation.

When the EN pin is connected to a logic low, the EL7532 is in the shut-down mode. All the control circuitry and both MOSFETs are off, and VOUT falls to zero. In this mode, the total input current is less than 1µA.

When the EN reaches logic HI, the regulator repeats the start-up procedure, including the soft-start function.

RSI/POR Function

When powering up, the open-collector Power-On-Reset output holds low for about 100ms after VO reaches the preset voltage. When the active-HI reset signal RSI is issued, POR goes to low immediately and holds for the same period of time after RSI comes back to LOW. The output voltage is unaffected. (Please refer to the timing diagram). When the function is not used, connect RSI to ground and leave open the pull-up resister R4 at POR pin.The POR output also serves as a 100ms delayed Power Good signal when the pull-up resister R4 is installed. The RSI pin needs to be directly (or indirectly through a resister R6) connected to Ground for this to function properly.

PWM Operation

In the PWM mode, the P channel MOSFET and N channel MOSFET always operate complementary. When the

PMOSFET is on and the NMOSFET off, the inductor current increases linearly. The input energy is transferred to the output and also stored in the inductor. When the P channel MOSFET is off and the N channel MOSFET on, the inductor current decreases linearly, and energy is transferred from the inductor to the output. Hence, the average current

through the inductor is the output current. Since the inductor and the output capacitor act as a low pass filter, the duty cycle ratio is approximately equal to VO divided by VIN.The output LC filter has a second order effect. To maintain the stability of the converter, the overall controller must be compensated. This is done with the fixed internally

compensated error amplifier and the PWM compensator. Because the compensations are fixed, the values of input and output capacitors are 10µF to 22µF ceramic. The

inductor is nominally 1.8µH, though 1.5µH to 2.2µH can be used.

VO

MIN25ns

100ms

POR

100ms

RSI

FIGURE 15.RSI & POR TIMING DIAGRAM

Output Voltage Selection

Users can set the output voltage of the converter with a resister divider, which can be chosen based on the following formula:

R2

VO=0.8×1+------R1

100% Duty Ratio Operation

EL7532 utilizes CMOS power FET's as the internal

synchronous power switches. The upper switch is a PMOS and lower switch a NMOS. This not only saves a boot capacitor, it also allows 100% turn-on of the upper PFET switch, achieving VO close to VIN. The maximum achievable VO is,

VO=VIN–(RL+RDSON1)×IO

Component Selection

Because of the fixed internal compensation, the component choice is relatively narrow. We recommend 10µF to 22µF multi-layer ceramic capacitors with X5R or X7R rating for both the input and output capacitors, and 1.5µH to 2.2µH inductance for the inductor.

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At extreme conditions (VIN < 3V, IO > 0.7A, and junction temperature higher than 75°C), input cap C1 is

recommended to be 22µF. Otherwise, if any of the above 3 conditions is not true, C1 can remain as low as 10µF.The RMS current present at the input capacitor is decided by the following formula:

VO×(VIN - VO)IINRMS=-----------------------------------------------×IO

VIN

Layout Considerations

The layout is very important for the converter to function properly. The following PC layout guidelines should be followed:

•Separate the Power Ground () and Signal Ground (); connect them only at one point right at the pins•Place the input capacitor as close to VIN and PGND pins as possible•Make the following PC traces as small as possible:-from LX pin to L-from CO to PGND

•If used, connect the trace from the FB pin to R1 and R2 as close as possible

•Maximize the copper area around the PGND pin

•Place several via holes under the chip to additional ground plane to improve heat dissipationThe demo board is a good example of layout based on this outline. Please refer to the EL7532 Application Brief.

This is about half of the output current IO for all the VO. This input capacitor must be able to handle this current.The inductor peak-to-peak ripple current is given as:

(VIN - VO)×VO

∆IIL=--------------------------------------------L×VIN×fS

•L is the inductance

•fS the switching frequency (nominally 1.5MHz)

The inductor must be able to handle IO for the RMS load current, and to assure that the inductor is reliable, it must handle the 3A surge current that can occur during a current limit condition.

Current Limit and Short-Circuit Protection

The current limit is set at about 3A for the PMOS. When a short-circuit occurs in the load, the preset current limit

restricts the amount of current available to the output, which causes the output voltage to drop below the preset voltage. In the meantime, the excessive current heats up the regulator until it reaches the thermal shut-down point.

Thermal Shut-Down

Once the junction reaches about 145°C, the regulator shuts down. Both the P channel and the N channel MOSFETs turn off. The output voltage will drop to zero. With the output MOSFETs turned off, the regulator will soon cool down. Once the junction temperature drops to about 130°C, the regulator will restart again in the same manner as the EN pin connects to logic HI.

Thermal Performance

The EL7532 is in a fused-lead MSOP10 package. Compared to the regular MSOP10 package, the fused-lead package provides lower thermal resistance. The typical θJA of 115°C/W (See Thermal Information section in spec table) can be improved by maximizing the copper area around the pins. A θJA of 100°C/W can be achieved on a 4-layer board and 125°C/W on a 2-layer board. Refer to Intersil’s Tech Brief, TB379, for more information on thermal resistance.

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MSOP Package Outline Drawing

NOTE:The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time withoutnotice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate andreliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may resultfrom its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

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