TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNSLAS220A –JUNE 1999DMaximum Throughput 400 KSPSDBuilt-In Reference and 8× FIFODDifferential/Integral Nonlinearity Error: DDD DAnalog Input Range 0 V to Supply VoltageDDDDWith 500 kHz BWHardware Controlled and ProgrammableSampling PeriodLow Operating Current (4 mA at 5.5 VExternal Ref, 6 mA at 5.5 V, Internal Ref)Power Down: Software/HardwarePower-Down Mode (1 µA Max, Ext Ref),Auto Power-Down Mode (1 µA, Ext Ref)Programmable Auto-Channel SweepD±1 LSBSignal-to-Noise and Distortion Ratio:69 dB, fi = 12 kHzSpurious Free Dynamic Range: 75 dB,fi = 12 kHzSPI/DSP-Compatible Serial Interfaces WithSCLK up to 20 MHzSingle Supply 5 VdcDW OR PW PACKAGE(TOP VIEW)D OR PW PACKAGE(TOP VIEW)SDOSDISCLKEOC/(INT)VCCA0A1A2A3A41234 567891020191817161514131211CSREFPREFMFSPWDNGNDCSTARTA7A6A5SDOSDISCLKEOC/(INT)VCCA0A1A21234 5678161514131211109CSREFPREFMFSPWDNGNDCSTARTA3descriptionThe TLC2558 and TLC2554 are a family of high-performance, 12-bit low power, 1.6 µs, CMOS analog-to-digitalconverters (ADC) which operate from a single 5 V power supply. These devices have three digital inputs anda 3-state output [chip select (CS), serial input-output clock (SCLK), serial data input (SDI), and serial data output(SDO)] that provide a direct 4-wire interface to the serial port of most popular host microprocessors (SPIinterface). When interfaced with a DSP, a frame sync (FS) signal is used to indicate the start of a serial dataframe.In addition to a high-speed A/D converter and versatile control capability, these devices have an on-chip analogmultiplexer that can select any analog inputs or one of three internal self-test voltages. The sample-and-holdfunction is automatically started after the fourth SCLK edge (normal sampling) or can be controlled by a specialpin, CSTART, to extend the sampling period (extended sampling). The normal sampling period can also beprogrammed as short (12 SCLKs) or as long (24 SCLKs) to accommodate faster SCLK operation popularamong high-performance signal processors. The TLC2558 and TLC2554 are designed to operate with very lowpower consumption. The power-saving feature is further enhanced with software/hardware/auto power downmodes and programmable conversion speeds. The converter uses the external SCLK as the source of theconversion clock to achieve higher (up to 1.6 µs when a 20 MHz SCLK is used) conversion speed. There is a4-V internal reference available. An optional external reference can also be used to achieve maximum flexibility.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright © 1999, Texas Instruments IncorporatedPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•1SLAS220A –JUNE 1999TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNfunctional block diagramVCC4 VReference REFPREFM2558A0A1A2A3A4A5A6A72554A0XA1XA2XA3XSDIFIFO12 Bit × 8Low Power12-BITSAR ADCConversionClockCFRAnalogMUXS/HCommandDecodeMUXSDOCMR (4 MSBs)SCLKCSFSCSTARTPWDNControl LogicEOC/(INT)GNDAVAILABLE OPTIONSPACKAGED DEVICESTA0°C to 70°C–40°C to 85°C20-TSSOP(PW)TLC2558CPWTLC2558IPW20-SOIC(DW)TLC2558CDWTLC2558IDW16-SOIC(D)TLC2554CDTLC2554ID16-TSSOP(PW)TLC2554CPWTLC2554IPW2POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNSLAS220A –JUNE 1999Terminal FunctionsTERMINALNAMEA0A1A2A3A0A1A2A3A4A5A6A7NO.TLC25546789TLC255867891011121320IAnalog signal inputs. The analog inputs are applied to these terminals and are internallymultiplexed. The driving source impedance should be less than or equal to 1 kΩ.For a source impedance greater than 1 kΩ, use the asynchronous conversion start signal CSTART(CSTART low time controls the sampling period) or program long sampling period to increase thesampling time.I/ODESCRIPTIONCS16IChip select. A high-to-low transition on the CS input resets the internal 4-bit counter, enables SDI,and removes SDO from 3-state within a maximum setup time. SDI is disabled within a setup timeafter the 4-bit counter counts to 16 (clock edges) or a low-to-high transition of CS whicheverhappens first. SDO is 3-stated after the rising edge of CS.CS can be used as the FS pin when a dedicated serial port is used.This terminal controls the start of sampling of the analog input from a selected multiplex channel.A high-to-low transition starts sampling of the analog input signal. A low-to-high transition puts theS/H in hold mode and starts the conversion. This input is independent from SCLK and works whenCS is high (inactive). The low time of CSTART controls the duration of the sampling period of theconverter (extended sampling).Tie this terminal to VCC if not used.End of conversion or interrupt to host processor.[PROGRAMMED AS EOC]: This output goes from a high-to-low logic level at the end of thesampling period and remains low until the conversion is complete and data are ready for transfer.EOC is used in conversion mode 00 only.[PROGRAMMED AS INT]: This pin can also be programmed as an interrupt output signal to thehost processor. The falling edge of INT indicates data are ready for output. The following CS↓ orFS↑ clears INT. The falling edge of INT puts SDO back to 3-state even if CS is still active.CSTART1014IEOC/(INT)44OFS1317IDSP frame sync input. Indication of the start of a serial data frame in or out of the device. If FSremains low at the falling edge of CS, SDI is not enabled. A high-to-low transition on the FS inputresets the internal 4-bit counter and enables SDI within a maximum setup time. SDI is disabledwithin a setup time after the 4-bit counter counts to 16 (clock edges) or a low-to-high transition ofCS whichever happens first. SDO is 3-stated after the 16th bit is presented.Tie this terminal to VCC if not used.Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are withrespect to GND.Both analog and reference circuits are powered down when this pin is at logic zero. The device canbe restarted by active CS or CSTART after this pin is pulled back to logic one.Input serial clock. This terminal receives the serial SCLK from the host processor. SCLK is usedto clock the input SDI to the input register. It is also used as the source of the conversion clock.Serial data input. The input data is presented with the MSB (D15) first. The first 4-bit MSBs,D(15–12) are decoded as one of the 16 commands (12 only for the TLC2554). All trailing blanksare filled with zeros. The configure write commands require an additional 12 bits of data. When FS is not used (FS =1), the first MSB (D15) is expected after the falling edge of CS and isshifted in on the rising edges of SCLK (after CS↓).When FS is used (typical with an active FS from a DSP) the first MSB (D15) is expected after thefalling edge of FS and is shifted in on the falling edges of SCLK.GNDPWDNSCLKSDI111232151632IIIIPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•3SLAS220A –JUNE 1999TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNTerminal Functions (Continued)TERMINALNAMESDONO.TLC25541TLC25581OThe 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance statewhen CS is high and after the CS falling edge and until the MSB (D15) is presented. The outputformat is MSB (D15) first.When FS is not used (FS = 1 at the falling edge of CS), the MSB (D15) is presented to the SDOpin after the CS falling edge, and successive data are available at the rising edge of SCLK.When FS is used (FS = 0 at the falling edge of CS), the MSB (D15) is presented to SDO after thefalling edge of CS and FS = 0 is detected. Successive data are available at the falling edge of SCLK.(This is typically used with an active FS from a DSP.)For conversion and FIFO read cycles, the first 12 bits are the result from the previous conversion(data) followed by 4 trailing zeros. The first four bits from SDO for CFR read cycles should beignored. The register content is in the last 12 bits. SDO is 3 stated after the 16th bit.REFMREFP14151819IIExternal reference input or internal reference decoupling.External reference input or internal reference decoupling. (Shunt capacitors of 10 µF and 0.1 µFbetween REFP and REFM.) The maximum input voltage range is determined by the differencebetween the voltage applied to this terminal and the REFM terminal when an external referenceis used.Positive supply voltageI/ODESCRIPTION VCC55Idetailed descriptionanalog inputs and internal test voltagesThe 4/8 analog inputs and three internal test inputs are selected by the analog multiplexer depending on thecommand entered. The input multiplexer is a break-before-make type to reduce input-to-input noise injectionresulting from channel switching.pseudo-differential/single-ended inputAll analog inputs can be programmed as single-ended or pseudo-differential mode. Pseudo-differential modeis enabled by setting CFR.D7 – 1. Only three analog input channels (or seven channels for TLC2558) areavailable for TLV2554 since one input (A1 for TLC2554 or A2 for TLC2558) is used as the MINUS input whenpseudo-differential mode is used. The minus input pin can have a maximum ±0.2 V ripple. This is normally usedfor ground noise rejection.converterThe TLC2554/58 uses a 12-bit successive approximation ADC and 2-bit resistor string. The CMOS thresholddetector in the successive-approximation conversion system determines each bit by examining the charge ona series of binary-weighted capacitors (see Figure 1). In the first phase of the conversion process, the analoginput is sampled by closing the SC switch and all ST switches simultaneously. This action charges all thecapacitors to the input voltage.4POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNSLAS220A –JUNE 1999SCconverter (continued)ThresholdDetectorTo OutputLatch512Node512REF+REF+REF+REF+REF+REF+256842112-BitR-StringDACREF–REF–STREF–STREF–STREF–STREF–STSTSTVIFigure 1. Simplified Model of the Successive-Approximation SystemIn the next phase of the conversion process the threshold detector begins identifying bits by identifying thecharge (voltage) on each capacitor relative to the reference (REFM) voltage. In the switching sequence, tencapacitors are examined separately until all ten bits are identified and the charge-convert sequence is repeated.In the first step of the conversion phase, the threshold detector looks at the first capacitor (weight = 512). Node512 of this capacitor is switched to the REFP voltage, and the equivalent nodes of all the other capacitors onthe ladder are switched to REFM. If the voltage at the summing node is greater than the trip point of the thresholddetector (approximately one-half the VCC voltage), a bit 0 is placed in the output register and the 512-weightcapacitor is switched to REFM. If the voltage at the summing node is less than the trip point of the thresholddetector, a bit 1 is placed in the register. The 512-weight capacitor remains connected to REFP through theremainder of the successive-approximation process. The process is repeated for the 1024-weight capacitor,the 128-weight capacitor, and so forth down the line until all bits are counted.With each step of the successive-approximation process, the initial charge is redistributed among thecapacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.serial interfaceINPUT DATA FORMATMSBD15–D12CommandD11–D0Configuration data fieldLSBInput data is binary. All trailing blanks can be filled with zeros.OUTPUT DATA FORMAT READ CFRMSBD15–D12Don’t careD11–D0Register contentLSBOUTPUT DATA FORMAT CONVERSION/READ FIFOMSBD15–D4Conversion resultD3–D0All zerosLSBPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•5SLAS220A –JUNE 1999TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNserial interface (continued)The output data format is either binary (unipolar straight binary) or 2s complement. binaryZero scale code = 000h, Vcode = VREFMFull scale code = FFFh, Vcode = VREFP – 1 LSB2’s complementMinus full scale code = 800h, Vcode = VREFMFull scale code = 7FFh, Vcode = VREFP – 1 LSBcontrol and timingstart of the cycle:DWhen FS is not used ( FS = 1 at the falling edge of CS), the falling edge of CS is the start of the cycle. Inputdata is shifted in on the rising edge, and output data changes on the falling edge of SCLK. This is typicallyused for a SPI microcontroller, although it can also be used for a DSP.data is shifted in on the falling edge, and output data changes on the rising edge of SCLK. This is typicallyused for a TMS320 DSP.DWhen FS is used ( FS is an active signal from a DSP), the falling edge of FS is the start of the cycle. Inputfirst 4-MSBs: the command register (CMR)The TLC2554/TLC2558 have a 4-bit command set (see Table 1) plus a 12-bit configuration data field. Most ofthe commands require only the first 4 MSBs, i.e. without the 12-bit data field.NOTE:The device requires a write CFR (configuration register) with 000h data (write A000h to the serialinput) at power up to initialize host select mode.The valid commands are listed in Table 1.Table 1. TLC2554/TLC2558 Command SetSDI D(15–12) BINARY, HEX0000b0001b0010b0011b0100b0101b0110b0111b1000b1001b1010b1011b1100b1101b1110b1111b0000h1000h2000h3000h4000h5000h6000h7000h8000h9000hA000h plus dataB000hC000hD000hE000hF000hplusdataF000h plus dataTLC2558 COMMANDSelect analog input channel 0Select analog input channel 1Select analog input channel 2Select analog input channel 3Select analog input channel 4Select analog input channel 5Select analog input channel 6Select analog input channel 7SW power down (analog + reference)Read CFR register data shown as SDO D(11–0)Write CFR followed by 12-bit dataSelect test, voltage = (REFP+REFM)/2Select test, voltage = REFMSelect test, voltage = REFPFIFO read, FIFO contents shown as SDO D(15–4), D(3–0) = 0000ReservedN/ASelect analog input channel 1N/ASelect analog input channel 2N/ASelect analog input channel 3N/ATLC2554 COMMANDSelect analog input channel 06POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNSLAS220A –JUNE 1999control and timing (continued)configurationConfiguration data is stored in one 12-bit configuration register (CFR) (see Table 2 for CFR bit definitions). Onceconfigured after first power up, the information is retained in the H/W or S/W power-down state. When the deviceis being configured, a write CFR cycle is issued by the host processor. This is a 16-bit write. If the SCLK stopsafter the first 8 bits are entered, then the next eight bits can be taken after the SCLK is resumed. The status ofthe CFR can be read with a read CFR command.Table 2. TLC2554/TLC2558 Configuration Register (CFR) Bit DefinitionsBITD(15–12)D11All zeros, nonprogrammableReference select0: External1: InternalOutput select0: Unipolar straight binary1: 2’s complementSample period select0: Short sampling 12 SCLKs (1x sampling time)1: Long sampling 24 SCLKs (2x sampling time)Conversion clock source select0: Conversion clock = SCLK1: Conversion clock = SCLK/2Input select0: Normal1: Pseudo differential CH A2(2558) or CH A1 (2554) is the differential inputConversion mode select00: Single shot mode01: Repeat mode10: Sweep mode11: Repeat sweep modeTLC2558Sweep auto sequence select00: 0–1–2–3–4–5–6–701: 0–2–4–6–0–2–4–610: 0–0–2–2–4–4–6–611: 0–2–0–2–0–2–0–2D2EOC/INT – pin function select0: Pin used as INT1: Pin used as EOCFIFO trigger level (sweep sequence length)00: Full (INT generated after FIFO level 7 filled)01: 3/4 (INT generated after FIFO level 5 filled)10: 1/2 (INT generated after FIFO level 3 filled)11: 1/4 (INT generated after FIFO level 1 filled)TLC2554Sweep auto sequence select00: N/A01: 0–1–2–3–0–1–2–310: 0–0–1–1–2–2–3–311: 0–1–0–1–0–1–0–1DEFINITIOND10D9D8D7D(6,5)D(4,3)†D(1,0)†These bits only take effect in conversion modes 10 and 11.samplingThe sampling period starts after the first 4 input data are shifted in if they are decoded as one of the conversioncommands. These are select analog input (channel 0 through 7) and select test (channel 1 through 3).POST OFFICE BOX 655303 DALLAS, TEXAS 75265•7SLAS220A –JUNE 1999TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNnormal sampling When the converter is using normal sampling, the sampling period is programmable. It can be 12 SCLKs (shortsampling) or 24 SCLKs (long sampling). Long sampling helps the input analog signal sampled to settle to 0.5LSB accuracy when input source resistance is high.extended samplingAn asynchronous (to the SCLK) signal, via dedicated hardware pin CSTART, can be used in order to have totalcontrol of the sampling period and the start of a conversion. This is extended sampling. The falling edge ofCSTART is the start of the sampling period. The rising edge of CSTART is the end of the sampling period andthe start of the conversion. This function is useful for an application that requires:DThe use of an extended sampling period to accommodate different input source impedance.DThe use of a faster I/O clock on the serial port but not enough sampling time is available due to the fixednumber of SCLKs. This could be due to a high input source impedance or due to higher MUX ON resistanceat lower supply voltage (refer to application information).Once the conversion is complete, the processor can initiate a read cycle using either the read FIFO commandto read the conversion result or simply select the next channel number for conversion. Since the device has avalid conversion result in the output buffer, the conversion result is simply presented at the serial data output.TLC2554/TLC2558 conversion modesThe TLC2554 and TLC2558 have four different conversion modes (mode 00, 01, 10, 11). The operation of eachmode is slightly different, depending on how the converter performs the sampling and which host interface isused. The trigger for a conversion can be an active CSTART (extended sampling), CS (normal sampling, SPIinterface), or FS (normal sampling, TMS320 DSP interface). When FS is used as the trigger, CS can be heldactive, i.e. CS does not need to be toggled through the trigger sequence. Different types of triggers should notbe mixed throughout the repeat and sweep operations. When CSTART is used as the trigger, the conversionstarts on the rising edge of CSTART. The minimum low time for CSTART is 800 ns. If an active CS or FS is usedas the trigger, the conversion is started after the 16th or 28th SCLK edge. Enough time (for conversion) shouldbe allowed between consecutive triggers so that no conversion is terminated prematurely.one shot mode (mode 00)One shot mode (mode 00) does not use the FIFO, and the EOC is generated as the conversion is in progress(or INT is generated after the conversion is done).repeat mode (mode 01)Repeat mode (mode 01) uses the FIFO. Once the programmed FIFO threshold is reached, the FIFO must beread, or the data is lost and the sequence starts over again. This allows the host to set up the converter andcontinue monitoring a fixed input and come back to get a set of samples when preferred. The first conversionmust start with a select command so an analog input channel can be selected.sweep mode (mode 10)Sweep mode (mode 10) also uses the FIFO. Once it is programmed in this mode, all of the channels listed inthe selected sweep sequence are visited in sequence. The results are converted and stored in the FIFO. Thissweep sequence may not be completed if the FIFO threshold is reached before the list is completed. This allowsthe system designer to change the sweep sequence length. Once the FIFO has reached its programmedthreshold, an interrupt (INT) is generated. The host must issue a read FIFO command to read and clear the FIFObefore the next sweep can start.8POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNSLAS220A –JUNE 1999TLC2554/TLC2558 conversion modes (continued)repeat sweep mode (mode 11)Repeat sweep mode (mode 11) works the same way as mode 10 except the operation has an option to continueeven if the FIFO threshold is reached. Once the FIFO has reached its programmed threshold, an interrupt (INT)is generated. Then two things may happen:1.The host may choose to act on it (read the FIFO) or ignore it. If the next cycle is a read FIFO cycle, all ofthe data stored in the FIFO is retained until it has been read in order.2.If the next cycle is not a read FIFO cycle, or another CSTART is generated, all of the content stored in theFIFO is cleared before the next conversion result is stored in the FIFO, and the sweep is continued.Table 3. TLC2554/TLC2558 Conversion ModeCONVERSIONMODEOne shotCFRD(6,5)00SAMPLINGTYPENormal•••••••••••••OPERATIONSingle conversion from a selected channelCS or FS to start select/sampling/conversion/readOne INT or EOC generated after each conversionHost must serve INT by selecting channel, and converting and reading the previous output.Single conversion from a selected channelCS to select/readCSTART to start sampling and conversionOne INT or EOC generated after each conversionHost must serve INT by selecting next channel and reading the previous output.Repeated conversions from a selected channelCS or FS to start sampling/conversionOne INT generated after FIFO is filled up to the thresholdHost must serve INT by either 1) (FIFO read) reading out all of the FIFO contents up to thethreshold, then repeat conversions from the same selected channel or 2) writing anothercommand(s) to change the conversion mode. If the FIFO is not read when INT is served, itis cleared.Same as normal sampling except CSTART starts each sampling and conversion when CS ishigh.One conversion per channel from a sequence of channelsCS or FS to start sampling/conversionOne INT generated after FIFO is filled up to the thresholdHost must serve INT by (FIFO read) reading out all of the FIFO contents up to the threshold,then write another command(s) to change the conversion mode.Same as normal sampling except CSTART starts each sampling and conversion when CS ishigh.Repeated conversions from a sequence of channelsCS or FS to start sampling/conversionOne INT generated after FIFO is filled up to the thresholdHost must serve INT by either 1) (FIFO read) reading out all of the FIFO contents up to thethreshold, then repeat conversions from the same selected channel or 2) writing anothercommand(s) to change the conversion mode. If the FIFO is not read when INT is served it iscleared.Same as normal sampling except CSTART starts each sampling and conversion when CS ishigh.ExtendedRepeat01NormalExtendedSweep10Normal••••••••••ExtendedRepeat sweep11NormalExtended•NOTE:Programming the EOC/INT pin as the EOC signal works for mode 00 only. The other three modes automatically generate an INT signalirrespective of whether EOC/INT is programmed.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•9SLAS220A –JUNE 1999TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNtiming diagrams The timing diagrams can be categorized into two major groups: nonconversion and conversion. Thenonconversion cycles are read and write (configuration). None of these cycles carry a conversion. Conversioncycles are those four modes of conversion.read cycle (read FIFO or read CFR)read CFR cycle:The read command is decoded in the first 4 clocks. SDO outputs the contents of the CFR after the 4th SCLK.1SCLKCSFSSDIINTEOC23456712131415161ID15ID14ID13ID12ID15SDOOD11OD10OD9OD4OD3OD2OD1OD0Figure 2. TLC2554/TLC2558 Read CFR Cycle (FS active)1SCLKCSFSSDIINTEOCSDOOD11OD10OD9OD4OD3OD2OD1OD0ID15ID14ID13ID12ID15ID1423456712131415161Figure 3. TLC2554/TLC2558 Read CFR Cycle (FS = 1)10POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNSLAS220A –JUNE 1999read cycle (read FIFO or read CFR) (continued)FIFO read cycleThe first command in the active cycle after INT is generated, if the FIFO is used, is assumed as the FIFO readcommand. The first FIFO content is output immediately before the command is decoded. If this command isnot a FIFO read, then the output is terminated but the first data in the FIFO is retained until a valid FIFO readcommand is decoded. Use of more layers of the FIFO reduces the time taken to read multiple data. This isbecause the read cycle does not generate EOC or INT nor does it carry out any conversion.1SCLKCSFSSDIINTEOCSDOOD11OD10OD9OD8OD7OD6OD5OD023456712131415161ID15ID14ID13ID12ID15ID14Figure 4. TLC2554/TLC2558 Continuous FIFO Read Cycle (FS = 1)(controlled by SCLK, SCLK can stop between each 16 SCLKs)POST OFFICE BOX 655303 DALLAS, TEXAS 75265•11SLAS220A –JUNE 1999TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNwrite cycle (write CFR) The write cycle is used to write to the configuration register CFR (with 12-bit register content). The write cycledoes not generate an EOC or INT nor does it carry out any conversion.1SCLKCSFSSDIINTEOCSDO23456712131415161ID15ID14ID13ID12ID11ID10ID9ID4ID3ID2ID1ID0ID15Figure 5. TLC2554/TLC2558 Write Cycle (FS active)1SCLKCSFSSDIINTEOCSDOID15ID14ID13ID12ID11ID10ID9ID4ID3ID2ID1ID0ID15ID1423456712131415161Figure 6. TLC2554/TLC2558 Write Cycle (FS = 1)12POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNSLAS220A –JUNE 1999conversion cyclesDSP/normal sampling1SCLKCSFS2345671213141516281SDIID15ID14ID13ID12ID15INTtsample (Long)tsample (Short)tconvEOCt convSDOOD11OD10OD9OD8OD7OD6OD5OD0Figure 7. Mode 00 Single Shot/Normal Sampling (FS signal used)1SCLKCSFS2345671213141516281SDIID15ID14ID13ID12ID15ID14INTtsample (Long)tsample (Short)tconvEOCt convSDOOD11OD10OD9OD8OD7OD6OD5OD0Figure 8. Mode 00 Single Shot/Normal Sampling (FS = 1, FS signal not used)POST OFFICE BOX 655303 DALLAS, TEXAS 75265•13SLAS220A –JUNE 1999TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNconversion cycles (continued)Select/ReadCycleCStsampleCSTARTSelect/ReadCycle FStconvertSDIINTEOCHi-Z†Previous ConversionResultHi-ZPrevious ConversionResultHi-ZSDO†This is one of the single shot commands. Conversion starts on next rising edge of CSTART.Figure 9. Mode 00 Single Shot/Extended Sampling (FS signal used, FS pin connected to TMS320 DSP)CS used as FS inputWhen interfacing with the TMS320 DSP using conversion mode 00, the FSR signal from the DSP may beconnected to the CS input if this is the only device on the serial port. This will save one output pin from the DSP.Output data is made available on the rising edge of SCLK and input data is latched on the rising edge of SCLKin this case.modes using the FIFO: modes 01, 10, 11 timingModes 01, 10, and 11 timing are very similar except for how and when the FIFO is read, how the device isconfigured, and how channel(s) are selected.Mode 01 (repeat mode) requires a two-cycle configuration where the first one sets the mode and the secondone selects the channel. Once the FIFO is filled up to the threshold programmed, it has the option to either readthe FIFO or configure for other modes. Therefore, the sequence is either configure: select : triggeredconversions : FIFO read : select : triggered conversions : FIFO read or configure : select : triggered conversions: configure : .... Each configure clears the FIFO and the action that follows the configure command depends onthe mode setting of the device.14POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNSLAS220A –JUNE 1999modes using the FIFO: modes 01, 10, 11 timing (continued)ConfigureSelectCSFStsampletconvertCSTART†§‡‡‡‡§tsampletconverttconverttsampleConversion #1From Channel 2Conversion #4From Channel 2SelectSDIINTSDOHi-ZRead FIFO#1Top of FIFO#2#3#4Next #1Hi-Z†Command = Configure write for mode 01, FIFO threshold = 1/2‡Command = Read FIFO, 1st FIFO read§Command = Select ch2.Figure 10. TLC2554/TLC2558 Mode 01 DSP Serial Interface (conversions triggered by FS)Conversion #1From Channel 2Conversion #4From Channel 2ConfigureSelectCSFS(DSP)Selecttsample(2)tsample(1)tsample(3)tsample(4)CSTARTtconvert(1)tconvert(2)tconvert(4)tconvert(3)SDIINTSDO†§‡‡‡‡§Hi-ZtSample(i) > = MIN(tSample)Read FIFO#1#2First FIFO Read#3#4Next #1Hi-Z†Command = Configure write for mode 01, FIFO threshold = 1/2‡Command = Read FIFO, 1st FIFO read§Command = Select ch2.Figure 11. TLC2554/TLC2558 Mode 01 µp/DSP Serial Interface (conversions triggered by CSTART)POST OFFICE BOX 655303 DALLAS, TEXAS 75265•15SLAS220A –JUNE 1999TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNmodes using the FIFO: modes 01, 10, 11 timing (continued) Mode 10 (sweep mode) requires reconfiguration at the start of each new sweep sequence. Once the FIFO isfilled up to the programmed threshold, the host has the option to either read the FIFO or configure for othermodes. Once the FIFO is read, the host must reconfigure the device before the next sweep sequence can bestarted. So the sequence is either configure : triggered conversions : FIFO read : configure. or configure :triggered conversions : configure : .... Each configure clears the FIFO and the action that follows the configurecommand depends on the mode setting of the device.Mode 11 (repeat sweep mode) requires one cycle configuration. This sweep sequence can be repeated withoutreconfiguration. Once the FIFO is filled up to the programmed threshold, the host has the option to either readthe FIFO or configure for other modes. So the sequence is either configure : triggered conversions : FIFO read: triggered conversions : FIFO read ... or configure : triggered conversions : configure : .... Each configure clearsthe FIFO and the action that follows the configure command depends on the mode setting of the device.ConversionFrom Channel 0ConversionFrom Channel 3ConversionFrom Channel 0ConversionFrom Channel 3ConfigureCStsample(3)tsample(2)tsample(1)FS(DSP)tconverttconvertCSTARTSDI†tSample(i) > = MIN(tSample)tsample(4)‡‡‡‡‡INTSDORepeatRead FIFO#1#2#3Top of FIFOFirst FIFO Read#4RepeatRead FIFO#1Second FIFO Read†Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0–1–2–3.‡Command = Read FIFOFigure 12. TLC2554/TLC2558 Mode 10/11 DSP Serial Interface (conversions triggered by FS)16POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNSLAS220A –JUNE 1999modes using the FIFO: modes 01, 10, 11 timing (continued)ConversionFrom Channel 0ConfigureCSFS(DSP)tsample(i) >= MIN (tsample)ConversionFrom Channel 3ConversionFrom Channel 0ConversionFrom Channel 3CSTARTtsample (1)tsample (2)tsample (3)tsample (4)tconvert‡‡‡‡‡tconvertSDIINTSDO†RepeatRead FIFO#1#2Top of FIFO#3#4RepeatRead FIFO#1Second FIFO ReadFirst FIFO Read†Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0–1–2–3.‡Command = Read FIFOFigure 13. TLC2554/TLC2558 Mode 10/11 DSP Serial Interface (conversions triggered by CSTART)ConversionFrom Channel 0ConfigureCStsample(1)tsample(2)ConversionFrom Channel 3ConversionFrom Channel 0ConversionFrom Channel 3tsample(3)tsample(4)tconverttconverttSample (i) > = MIN(tSample)CSTART†‡‡‡‡‡SDIINTSDORead FIFORepeat#1#2#3Top of FIFOFirst FIFO Read#4RepeatRead FIFO#1Second FIFO Read†Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0–1–2–3.‡Command = Read FIFOFigure 14. TLC2554/TLC2558 Mode 00/11 µp Serial Interface (conversions triggered by CS)POST OFFICE BOX 655303 DALLAS, TEXAS 75265•17SLAS220A –JUNE 1999TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNFIFO operationSerial12-BIT×8FIFOADC76543210 ODFIFO FullFIFO 1/2 FullFIFO 3/4 FullFIFO 1/4 FullFIFO Threshold PointerFigure 15. TLC2554/TLC2558 FIFOThe device has an 8 layer FIFO that can be programmed for different thresholds. An interrupt is sent to the hostafter the preprogrammed threshold is reached. The FIFO can be used to store data from either a fixed channelor a series of channels based on a preprogrammed sweep sequence. For example, an application may requireeight measurements from channel 3. In this case, the FIFO is filled with 8 data sequentially taken from channel3. Another application may require data from channel 0, channel 2, channel 4, and channel 6 in an orderlymanner. Therefore, the threshold is set for 1/2 and the sweep sequence 0–2–4–6–0–2–4–6 is chosen. Aninterrupt is sent to the host as soon as all four data are in the FIFO.SCLK and conversion speedThere are multiple ways to adjust the conversion speed. The maximum equivalent conversion clock (fSCLK/DIV)should not exceed 10 MHz.DThe SCLK is used as the source of the conversion clock and 14 conversion clocks are required to completea conversion plus 4 SCLKs overhead.The devices can operate with an SCLK up to 20 MHz for the supply voltage range specified. The clockdivider provides speed options appropriate for an application where a high speed SCLK is used for fasterI/O. The total conversion time is 14 ×(DIV/fSCLK) where DIV is 1 or 2. For example a 20-MHz SCLK with thedivide by 2 option produces a {14 × (2/20 M) + 4× (1/20 MHz)} = 1.6 µs conversion time.DAuto power down can be used. This mode is always on. If the device is not accessed (by CS or CSTART),reference voltagethe converter is powered down to save power. The built-in reference is left on in order to quickly resumeoperation within one half SCLK period. This provides unlimited choices to trade speed with power savings.The device has a built-in reference with a level of 4 V. If the internal reference is used, REFP is set to 4 V andREFM is set to 0 V. An external reference can also be used through two reference input pins, REFP and REFM,if the reference source is programmed as external. The voltage levels applied to these pins establish the upperand lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively. The values ofREFP, REFM, and the analog input should not exceed the positive supply or be lower than GND consistent withthe specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to orhigher than REFP and at zero when the input signal is equal to or lower than REFM.18POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNSLAS220A –JUNE 1999FIFO operation (continued)power downWriting 8000h to the device puts the device into a software power-down state. For a hardware power down, thededicated PWDN pin provides another way to power down the device asynchronously. These two power-downmodes power down the entire device including the built-in reference to save power. It requires 20 ms to resumefrom either a software or hardware power down.Auto power down mode is always enabled. This mode maintains the built-in reference if an internal referenceis used, so resumption is fast enough to be used between cycles.The configuration register is not affected by any of the power down modes but the sweep operation sequencehas to be started over again. All FIFO contents are cleared by the power-down modes.power up and initializationInitialization requires:1.Determine processor type by writing A000h to the TLC2554/582.Configure the deviceThe first conversion after power up or resuming from power down is not valid.absolute maximum ratings over operating free-air temperature (unless otherwise noted)†Supply voltage range, GND to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 VAnalog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 VReference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3 VDigital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 VOperating virtual junction temperature range, TJ –40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°COperating free-air temperature range, TA:TLC2554/58C 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 70°CTLC2554/58I –40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 85°CStorage temperature range, Tstg –65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.recommended operating conditionsMINSupply voltage, VCCPositive external reference voltage input, VREFP (see Note 1)Negative external reference voltage input, VREFM (note Note 1)Differential reference voltage input, VREFP – VREFM (see Note 1)Analog input voltage (see Note 1)High level control input voltage, VIHLow-level control input voltage, VILRise time, for CS, CSTART SDI at 0.5 pF, tr(I/O)Fall time, for CS, CSTART SDI at 0.5 pF, tf(I/O)Rise time, for INT, EOC, SDO at 30 pF, tr(Output)Fall time, for INT, EOC, SDO at 30 pF, tf(Output)4.520202.10.6 4.762.912.432.3NOM5MAX5.5VCC2VCCVCC+0.2VCCUNITVVVVVVVnsnsnsnsNOTE 1:When binary output format is used, analog input voltages greater than that applied to REFP convert as all ones (111111111111), whileinput voltages less than that applied to REFM convert as all zeros (000000000000). The device is functional with reference down to2 V (VREFP – VREFM –1); however, the electrical specifications are no longer applicable.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•19SLAS220A –JUNE 1999TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNrecommended operating conditions (continued)MINTransition time, for FS, SCLK, SDI, tt(CLK)Setup time, CS falling edge before SCLK rising edge (FS=1) or before SCLK falling edge (when FS is active),tsu(CS-SCLK)Hold time, CS rising edge after SCLK rising edge (FS=1) or after SCLK falling edge (when FS is active),th(SCLK-CS)Delay time, delay from CS falling edge to FS rising edge, td(CSL-FSH)Delay time, delay time from 16th SCLK falling edge to CS rising edge (FS is active), td(SCLK16F-CSH)Setup time, FS rising edge before SCLK falling edge, tsu(FSH-SCLKF)Hold time, FS hold high after SCLK falling edge, th(FSH-SCLKF)Pulse width, CS high time, twH(CS)SCLK cycle time, VCC = 2.7 V to 3.6V, tc(SCLK)SCLK cycle time, VCC = 4.5 V to 5.5V, tc(SCLK)Pulse width, SCLK low time, twL(SCLK)Pulse width, SCLK high time, twH(SCLK)Setup time, SDI valid before falling edge of SCLK (FS is active) or the rising edge of SCLK (FS=1),tsu(DI-SCLK)Hold time, SDI hold valid after falling edge of SCLK (FS is active) or the rising edge of SCLK (FS=1),th(DI-SCLK)Delay time, delay from CS falling edge to SDO valid, td(CSL-DOV)Delay time, delay from FS falling edge to SDO valid, td(FSL-DOV)Delay time, delay from SCLK rising edge (FS is active) or SCLK falling edge (FS=1) SDO valid, td(CLK-DOV)Delay time, delay from CS rising edge to SDO 3-stated, td(CSH-DOZ)Delay time, delay from 16th SCLK falling edge (FS is active) or the 16th rising edge (FS=1) to EOC fallingedge, td(CLK-EOCL)Delay time, delay from EOC rising edge to SDO 3-stated if CS is low, td(EOCH-DOZ)Delay time, delay from 16th SCLK rising edge to INT falling edge (FS =1) or from the 16th falling edge SCLKto INT falling edge (when FS active), td(SCLK-INTL)Delay time, delay from CS falling edge to INT rising edge, td(CSL-INTH)Delay time, delay from CS rising edge to CSTART falling edge, td(CSH-CSTARTL)Delay time, delay from CSTART rising edge to EOC falling edge, td(CSTARTH-EOCL)Pulse width, CSTART low time, twL(CSTART)Delay time, delay from CS rising edge to EOC rising edge, td(CSH-EOCH)Delay time, delay from CSTART rising edge to CSTART falling edge, td(CSTARTH-CSTARTL)Delay time, delay from CSTART rising edge to INT falling edge, td(CSTARTH-INTL)OperatingfreeairtemperatureTAOperating free-air temperature, TTLC2554C/TLC2558CTLC2554I/TLC2558I0.510067502020303025511111 1 110010.813.63.50–4050 7085 25 2525 25 25503.5 50 500.50.550.50.50.57NOMMAXUNITSCLKSCLKnsSCLKsSCLKsSCLKsSCLKsnsnsnsnsnsnsnsnsnsnsnsnsnsµsnsnsnsµsnsµsµs_C NOTE 2:This is the time required for the clock input signal to fall from VIH max or to rise from VILmax to VIHmin. In the vicinity of normal roomtemperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition applications where thesensor and A/D converter are placed several feet away from the controlling microprocessor.20POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNSLAS220A –JUNE 19995.5 V, SCLK frequency = 20 MHz at 5 V, (unless otherwise noted)PARAMETERVOHVOLIOZIIHIILICCICCHigh-level output voltageLow-level output voltageOsaeouucueOff-state output current(high-impedance-state)High-level input currentLow-level input currentOeagsuycue,oasaOperating supply current, normal samplingg(short)OperatingsupplycurrentextendedsamplingOperating supply current, extended samplingInternal reference supply currentelectrical characteristics over recommended operating free-air temperature range, VCC = VREFP = 4.5 V toTEST CONDITIONSVCC = 5.5 V, IOH = –20 µA at 30 pF loadVCC = 5.5 V, IOL = 20 µA at 30 pF loadVO = VCCVO = 0VI = VCCVI = 0 VCS at 0 V, Ext refCS at 0 V, Int refCS at 0 V, Ext refCS at 0 V, Int refVCC = 4.5 V to 5.5 VVCC = 4.5 V to 5.5 VVCC = 4.5 V to 5.5 VVCC = 4.5 V to 5.5 V1.922CSVCCCS = V1–10.005–0.005MIN2.40.42.5-2.52.52.546TYP†MAXUNITVVµAµAµAmAmAmAmAmACS at 0 V, VCC = 4.5 V to 5.5 VFor all digital inputs, 0≤ VI ≤ 0.3 V or VI ≥ VCC– 0.3 V,SCLK = 0, VCC = 4.5 V to 5.5 V, Ext clockFor all digital inputs,0≤ VI ≤ 0.3 V or VI ≥ VCC– 0.3 V,SCLK = 0, VCC = 4.5 V to 5.5 V,Ext clock, Ext refSelected channel at VCCSelected channel at 0 VVREFP = VCC = 5.5 V, VREFM = GNDAnalog inputsControl InputsVCC = 5.5 V4550.1ICC(PD)Power-down supply current1µAICC(AUTOPWDN)Auto power-down current5‡µASelectedchannelleakagecurrentSelected channel leakage currentMaximum static analog reference current intoREFP (use external reference)CiZiInputcapacitanceInput capacitanceInput MUX ON resistance1–115025500µAµApFΩ†All typical values are at VCC = 5 V, TA = 25°C.‡800 µA if internal reference is used.ac specificationsPARAMETERSINADTHDENOBSFDRSignal-to-noise ratio +distortionTotal harmonic distortionEffective number of bitsSpurious free dynamic rangeFull power bandwidth, –3 dBFull power bandwidth, –1 dBTEST CONDITIONSfI = 12 kHz at 400 KSPSfI = 12 kHz at 400 KSPSfI = 12 kHz at 400 KSPSfI = 12 kHz at 400 KSPSMIN69TYP71–8211.6–841500–75–76MAXUNITdBdBBitsdBMHzkHzAnalog inputPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•21SLAS220A –JUNE 1999TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNreference specifications (0.1 µF and 10 µF between REFP and REFM pins)PARAMETERReference input voltage, REFPInputimpedanceInput impedanceInput voltage difference, REFP – REFMInternal reference voltage,REFP – REFMInternal reference start up timeReference temperature coefficientVCC = 4.5 VVCC = 5.5 V=55VVCC = 4.5 VVCC = 5.5 VVCC = 5.5 VVCC = 4.5 VCS = 1,CS = 0,SCLK = 0, (off)SCLK = 20 MHz (on)100202Reference select = internal10 µF3.854201625VCC4.15TEST CONDITIONSMINTYPMAXVCCUNITVMΩkΩVVms40PPM/°C operating characteristics over recommended operating free-air temperature range, VCC = VREFP = 4.5 V,SCLK frequency = 20 MHz (unless otherwise noted)PARAMETERIntegral linearity error (INL) (see Note 4)Differential linearity error (DNL)EOEGETOffset error (see Note 5)Gain error (see Note 5)Total unadjusted error (see Note 6)SDI = B000hSelf-test output code (see Table 1 and Note 7)SDI = C000hSDI = D000htconvtsamplett(I/O)Conversion timeSampling timeTransition time for EOC, INTExternal SCLKAt 1 kΩ60050800h(2048D)000h(0D)FFFh(4095D)(14XDIV)fSCLKnsnsSee Note 3See Note 3See Note 3±1TEST CONDITIONSMINTYP†MAX±1±1±2.5±2±2UNITLSBLSBLSBLSBLSBtt(CLK)Transition time for SDI, SDO25ns†All typical values are at TA = 25°C.NOTES:3.Analog input voltages greater than that applied to REFP convert as all ones (111111111111), while input voltages less than thatapplied to REFM convert as all zeros (0000000000). The device is functional with reference down to 2 V (VREFP – VREFM);however, the electrical specifications are no longer applicable.4.Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.5.Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the differencebetween 111111111111 and the converted output for full-scale input voltage.6.Total unadjusted error comprises linearity, zero, and full-scale errors.7.Both the input data and the output codes are expressed in positive logic.22POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNSLAS220A –JUNE 1999PARAMETER MEASUREMENT INFORMATIONtt(I/O)90%50%10%td(CSL-FSH)tt(I/O)VIHtwH(CS)CSVILVIHVILFStsu(FSH-SCLKF)twL(SCLK)tsu(CS-SCLK)th(SCLK-CS)116th(FSH-SCLKF)twH(SCLK)td(SCLK16F-CSH)VIHVILSCLKtc(SCLK)tsu(DI-CLK)th(DI-CLK)SDIVIHID15ID1td(FSL-DOV)td(CSL-DOV)VILtd(CLK-DOV)Hi-ZVOHVOLSDOtd(CLK-EOCL)td(EOCH–DOZ)VOHEOCtd(SCLK-INTL)td(CSL-INTH)VOLVOHINTVOLFigure 16. Critical Timing (normal sampling, FS is active)POST OFFICE BOX 655303 DALLAS, TEXAS 75265•23SLAS220A –JUNE 1999TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNPARAMETER MEASUREMENT INFORMATIONVIHCStd(CSH-CSTARTL)twL(CSTART)CSTARTtd(CSH-EOCH)tt(I/O)EOCtd(CSTARTH-EOCL)td(EOCH-INTL)td(CSL-INTH)INTVOHVOLtt(I/O)tconvertVOHVOLVIHVILVIL Figure 17. Critical Timing (extended sampling, single shot)VIHCStd(CSL-CSTARTL)CSTARTtd(CSH-EOCH)tt(I/O)EOCtd(CSTARTH-EOCL)td(CSTARTH-INTL)td(CSL-INTH)VOL90%50%10%tt(I/O)VOHtwL(CSTART)td(CSTARTH–CSTARTL)VIHVILVILVOHVOLINTFigure 18. Critical Timing (extended sampling, repeat/sweep/repeat sweep)24POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNSLAS220A –JUNE 1999PARAMETER MEASUREMENT INFORMATIONtt(I/O)CStsu(CS-SCLK)twL(SCLK)twH(SCLK)SCLKtc(SCLK)tsu(DI-CLK)SDIID15ID1th(DI-CLK)VIHtt(I/O)VIHtwH(CS)td(SCLK16F-CSH)tt(CLK)116VILVIHVILVILtd(CLK-DOV)Hi-Ztd(EOCH-DOZ)VOHVOHVOLtd(CSL-DOV)SDOHi-ZOD15OD1OD0td(CLK-EOCL)ECOtd(SCLK-INTL)INTVOLtd(CSL-INTH)VOHVOLFigure 19. Critical Timing (normal sampling, FS = 1)POST OFFICE BOX 655303 DALLAS, TEXAS 75265•25SLAS220A –JUNE 1999TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNTYPICAL CHARACTERISTICSINTEGRAL NONLINEARITYvsTEMPERATURE0.55VCC = 5 V,Internal Reference = 4 V,SCLK = 20 MHz,Single Shot,Short Sample,Mode 00 µP mode0.5DNL – Differential Nonlinearity – LSB0.450.40.350.30.250.20.150.1–40VCC = 5 V,Internal Reference = 4 V,SCLK = 20 MHz,Single Shot,Short Sample,Mode 00 µP mode25TA – Temperature – °C85 DIFFERENTIAL NONLINEARITYvsTEMPERATUREINL – Integral Nonlinearity – LSB0.530.510.490.470.45–4025TA – Temperature – °C85Figure 20OFFSET ERRORvsTEMPERATURE1.71.61.51.41.31.21.110.90.80.70.60.50.40.30.20.10–40VCC = 5 V,External Reference = 4 V,SCLK = 20 MHz,Single Shot,Short Sample,Mode 00 µP mode25TA – Temperature – °C85Gain Error – LSB0–0.5–1–1.5–2–2.5–3–3.5–4–4.5–5–40Figure 21GAIN ERRORvsTEMPERATUREOffset Error – LSBVCC = 5 V,External Reference = 4 V,SCLK = 20 MHz,Single Shot,Short Sample,Mode 00 µP mode25TA – Temperature – °C85Figure 22Figure 2326POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNSLAS220A –JUNE 1999TYPICAL CHARACTERISTICSSUPPLY CURRENTvsTEMPERATURE43.93.8Supply Current – mA3.73.63.53.43.33.23.13–4025TA – Temperature – °C85VCC = 5.5 V,External Reference = 4 V,SCLK = 20 MHz,Single Shot,Short Sample,Mode 00 µP mode0.50.40.3Power Down – µA0.20.10–0.1–0.2–0.3–0.4–0.5–4025TA – Temperature – °C85VCC = 5.5 V,External Reference = 4 V,SCLK = 20 MHz,Single Shot,Short Sample,Mode 00 µP modePOWER DOWN CURRENTvsTEMPERATUREFigure 24INTEGRAL NONLINEARITYvsSAMPLESINL – Integral Nonlinearity – LSB1.00.80.60.40.2–0.0–0.2–0.4–0.6–0.8–1.002048SamplesVCC = 5 V, External Reference = 5 V, SCLK = 20 MHz,Single Shot, Short Sample, Mode 00 DSP ModeFigure 254096Figure 26POST OFFICE BOX 655303 DALLAS, TEXAS 75265•27SLAS220A –JUNE 1999TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNTYPICAL CHARACTERISTICSDIFFERENTIAL NONLINEARITYvsSAMPLES1.00.80.60.40.2–0.0–0.2–0.4–0.6–0.8–1.002048Samples4096VCC = 5 V, External Reference = 5 V, SCLK = 20 MHz,Single Shot, Short Sample, Mode 00 DSP Mode DNL – Differential Nonlinearity – LSBFigure 27INTEGRAL NONLINEARITYvsSAMPLESVCC = 5 V, Internal Reference = 4 V, SCLK = 20 MHz,Single Shot, Short Sample, Mode 00 DSP ModeINL – Integral Nonlinearity – LSB1.00.80.60.40.2–0.0–0.2–0.4–0.6–0.8–1.002048Samples4096Figure 2828POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNSLAS220A –JUNE 1999TYPICAL CHARACTERISTICSDIFFERENTIAL NONLINEARITYvsSAMPLES1.00.80.60.40.2–0.0–0.2–0.4–0.6–0.8–1.002048Samples4096VCC = 5 V, Internal Reference = 4 V, SCLK = 20 MHz,Single Shot, Short Sample, Mode 00 DSP ModeDNL – Differential Nonlinearity – LSBFigure 29FAST POURIER TRANSFORMvsFREQUENCY0–20Magnitude – dB–40–60–80–100–120–140050100f – Frequency – kHz150200AIN = 50 kHzVCC = 5 V, Channel 0External Reference = 4 VSCLK = 20 MHzSingle Shot, Short SampleMode 00 DSP ModeFigure 30POST OFFICE BOX 655303 DALLAS, TEXAS 75265•29SLAS220A –JUNE 1999TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNTYPICAL CHARACTERISTICSSIGNAL-TO-NOISE + DISTORTIONvsINPUT FREQUENCY80SINAD – Signal-to-Noise + Distortion – dB75706560555045400100f – Frequency – kHz200ENOB – Effective Number of Bits – BITSVCC = 5 V, External Reference = 4 V,SCLK = 20 MHz, Single Shot, ShortSample, Mode 00 DSP Mode12.0011.8011.6011.4011.2011.0010.8010.6010.4010.2010.009.809.609.409.209.000100f – Frequency – kHz200VCC = 5 V, External Reference = 4 V,SCLK = 20 MHz, Single Shot,Short Sample, Mode 00 DSP Mode EFFECTIVE NUMBER OF BITSvsINPUT FREQUENCYFigure 31TOTAL HARMONIC DISTORTIONvsINPUT FREQUENCY–50VCC = 5 V, External Reference = 4 V,SCLK = 20 MHz, Single Shot,Short Sample, Mode 00 DSP Mode0Figure 32SPURIOUS FREE DYNAMIC RANGEvsINPUT FREQUENCYTHD – Total Harmonic Distortion – dBSpurious Free Dynamic Range – dB–55–20VCC = 5 V, External Reference = 4 V,SCLK = 20 MHz, Single Shot,Short Sample, Mode 00 DSP Mode–60–40–65–60–70–75–80–800255075100125150f – Frequency – kHz175200–1000255075100125150175200f – Frequency – kHzFigure 33Figure 3430POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNSLAS220A –JUNE 1999PRINCIPLES OF OPERATION1111111111See Notes A and B11111111101111111101VFS NomVFT = VFS – 1/2 LSB1000000001100000000001111111114095VFS40944093Digital Output Code20492048Step31VZT =VZS + 1/2 LSB2047VZS00000000100000000001000000000002104.91520.00060.00120.00242.45642.45762.45884.90564.91344.9104VI – Analog Input Voltage – VNOTES:A.This curve is based on the assumption that Vref+ and Vref– have been adjusted so that the voltage at the transition from digital 0 to1 (VZT) is 0.0006 V, and the transition to full scale (VFT) is 4.9134 V, 1 LSB = 1.2 mV.B.The full scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) isthe step whose nominal midstep value equals zero.Figure 35. Ideal 12-Bit ADC Conversion Characteristicsvcc10 kΩXFTXDRXDCLKRCLKXTMS320 DSPBIOFSRFSXCSSDISDOVDDAINSCLKTLC2554/TLC2558FSGNDINTFigure 36. Typical Interface to a TMS320 DSPPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•SLAS220A –JUNE 1999TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNPRINCIPLES OF OPERATIONsimplified analog input analysis Using the equivalent circuit in Figure 39, the time required to charge the analog input capacitance from 0 to VSwithin 1/2 LSB can be derived as follows.The capacitance charging voltage is given by:Vc+VsWhereǓǓǒ1–EXPǒRt–tc Ci(1)Rt = Rs + Zitc = Cycle timeThe input impedance Zi is 0.5 kΩ at 5 V. The final voltage to 1/2 LSB is given by:VC(1ń2LSB)+VS–VSǓǒ8192(2)Equating equation 1 to equation 2 and solving for cycle time tc gives:Vs–VSǓ+Vsǒ1–EXPǒ–tcǓǓǒ8192Rt Ci(3)and time to change to 1/2 LSB (minimum sampling time) is:tch(1ń2LSB)+Rt Ci In(8192)WhereIn(8192) = 9.011Therefore, with the values given, the time for the analog input signal to settle is:tch(1ń2LSB)+(Rs)0.5kW) Ci In(8192)(4)This time must be less than the converter sample time shown in the timing diagrams. This is 12× SCLKs (if thesampling mode is short normal sampling mode).tch(1ń2LSB)v12 1f(SCLK)(5)Therefore the maximum SCLK frequency is:maxƪf(SCLK)ƫ+1212+ǒǓ[In(8192) Rt Ci]tch1ń2LSB(6)32POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNSLAS220A –JUNE 1999PRINCIPLES OF OPERATIONDriving Source†RsVSriVCCiTLC2554/58VI= Input Voltage at AINVS= External Driving Source VoltageRs= Source Resistanceri= Input Resistance (MUX on Resistance)Ci= Input CapacitanceVC= Capacitance Charging VoltageVI†Driving source requirements:•Noise and distortion for the source must be equivalent to the resolution of the converter.•Rs must be real at the input frequency.Figure 37. Equivalent Input Circuit Including the Driving Sourcemaximum conversion throughputFor a supply voltage of 5 V, if the source impedance is less than 1 kΩ, and the ADC analog input capacitanceCi is less than 50 pF, this equates to a minimum sampling time tch(0.5 LSB) of 0.676 µs. Since the samplingtime requires 12 SCLKs, the fastest SCLK frequency is 12/tch = 18 MHz.The minimal total cycle time is given as:tc+tcommand)tch)tconv)td(EOCH–CSL)+4 +16 1)1.7ms+2.59ms18MHz11)12 )1.6ms)0.1msf(SCLK)f(SCLK)This is equivalent to a maximum throughput of 386 KSPS. The throughput can be even higher with a smallersource impedance.When source impedance is 100 Ω, the minimum sampling time becomes:tch(1ń2LSB)+Rt Ci In(8192)+0.27msThe maximum SCLK frequency possible is 12/tch = 44 MHz. Then a 20 MHz clock (maximum SCLK frequencyfor the TLC2554/2548 ) can be used. The minimal total cycle time is then reduced to:tc+tcommand)tch)tconv)td(EOCH–CSL)+4 +0.8ms)1.6ms)0.1ms+2.5ms11)12 )1.6ms)0.1msf(SCLK)f(SCLK)The maximum throughput is 1/2.5 µs = 400 KSPS for this case.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•33SLAS220A –JUNE 1999TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNPRINCIPLES OF OPERATIONpower down calculationsi(AVERAGE) = (fS/fSMAX) × i(ON) + (1–fS/fSMAX) × i(OFF)CASE 1: If VDD = 3.3 V, auto power down, and an external reference is used: ffS+10kHz+200kHzSMAXi(ON)+X1mAoperatingcurrentandi(OFF)+X1mAautopower-downcurrentsoi(AVERAGE)+0.05 1000mA)0.95 1mA+51mACASE 2: Now if software power down is used, another cycle is needed to shut it down.ffS+20kHz+200kHzSMAXi(ON)+X1mAoperatingcurrentandi(OFF)+X1mApower-downcurrentsoi(AVERAGE)+0.1 1000mA)0.9 1mA+101mAIn reality this will be less since the second conversion never happened. It is only the additional cycle to shut downthe ADC.34POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNSLAS220A –JUNE 1999PRINCIPLES OF OPERATIONCASE 3: Now if the hardware power down is used.ffS+10kHz+200kHzSMAXi(ON)+X1mAoperatingcurrentandi(OFF)+X1mApower-downcurrentsoi(AVERAGE)+0.05 1000mA)0.95 1mA+51mAdifference between modes of conversionThe major difference between sweep mode (mode 10) and repeat sweep mode (mode 11) is that the sweepsequence ends after the FIFO is filled up to the programmed threshold. The repeat sweep can either dump theFIFO (by ignoring the FIFO content but simply reconfiguring the device) or read the FIFO and then repeat theconversions on the the same sequence of the channel as before.FIFO reads are expected after the FIFO is filled up to the threshold in each case. Mode 10 – the device allowsonly FIFO read or CFR read or CFR write to be executed. Any conversion command is ignored. In the case ofmode 11, in addition to the above commands, conversion commands are also executed , i.e. the FIFO is clearedand the sweep sequence is restarted.Both single shot and repeat modes require selection of a channel after the device is configured for these modes.Single shot mode does not use the FIFO, but repeat mode does. When the device is operating in repeat mode,the FIFO can be dumped (by ignoring the FIFO content and simply reconfiguring the device) or the FIFO canbe read and then the conversions repeated on the same channel as before. However, the channel has to beselected first before any conversion can be carried out. The devices can be programmed with the followingsequences for operating in the different modes that use a FIFO:POST OFFICE BOX 655303 DALLAS, TEXAS 75265•35SLAS220A –JUNE 1999TLC2554, TLC25585-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWNPRINCIPLES OF OPERATIONdifference between modes of conversion (continued)REPEAT:Configure FIFO Depth=4 /CONV Mode 01Select Channel/1st Conv (CS or CSTART)2nd Conv (CS or CSTART)3rd Conv (CS or CSTART)4th Conv (CS or CSTARTFIFO READ 1FIFO READ 2FIFO READ 3FIFO READ 4Select Channel1st Conv (CS or CSTART)2nd Conv (CS or CSTART)3rd Conv (CS or CSTART)4th Conv (CS or CSTARTSWEEP:Configure FIFO Depth=4 SEQ=1–2–3–4/CONV Mode 10conv ch 1 (CS/CSTART)conv ch 2 (CS/CSTART)conv ch 3 (CS/CSTART)conv ch 4 (CS/CSTARTFIFO READ ch 1 resultFIFO READ ch 2 resultFIFO READ ch 3 resultFIFO READ ch 4 resultConfigure (not required if same sweep sequence is to be used again)REPEAT SWEEP:Configure FIFO Depth=4 SWEEP SEQ=1-2-3-4/CONV Mode 11conv ch 1 (CS/CSTART)conv ch 2 (CS/CSTART)conv ch 3 (CS/CSTART)conv ch 4 (CS/CSTARTFIFO READ ch 1 resultFIFO READ ch 2 resultFIFO READ ch 3 resultFIFO READ ch 4 resultconv ch 1 (CS/CSTART)conv ch 2 (CS/CSTART)conv ch 3 (CS/CSTART)conv ch 4 (CS/CSTART 36POST OFFICE BOX 655303 DALLAS, TEXAS 75265•PACKAGEOPTIONADDENDUM
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2-Mar-2009
PACKAGINGINFORMATION
OrderableDeviceTLC2554CDTLC2554CDG4TLC2554IDTLC2554IDG4TLC2554IPWTLC2554IPWG4TLC2554QDTLC2554QDRTLC2558CDWTLC2558CDWG4TLC2558CPWTLC2558CPWG4TLC2558IDWTLC2558IDWG4TLC2558IPWTLC2558IPWG4TLC2558IPWRTLC2558IPWRG4TLC2558QDWTLC2558QDWR
(1)
Status(1)ACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEPREVIEWPREVIEWACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVE
PackageTypeSOICSOICSOICSOICTSSOPTSSOPSOICSOICSOICSOICTSSOPTSSOPSOICSOICTSSOPTSSOPTSSOPTSSOPSOICSOIC
PackageDrawing
DDDDPWPWDDDWDWPWPWDWDWPWPWPWPWDWDW
PinsPackageEcoPlan(2)
Qty1616161616161616202020202020202020202020
2525707025257070404040409090
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
TBDTBDGreen(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
Lead/BallFinishCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCallTICallTICUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCallTICallTI
MSLPeakTemp(3)Level-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMCallTICallTI
Level-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMCallTICallTI
2000Green(RoHS&
noSb/Br)2000Green(RoHS&
noSb/Br)
TBDTBD
Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)
EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Addendum-Page1
PACKAGEOPTIONADDENDUM
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2-Mar-2009
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)
(3)
MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
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Addendum-Page2
PACKAGEMATERIALSINFORMATION
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TAPEANDREELINFORMATION
*Alldimensionsarenominal
Device
PackagePackagePinsTypeDrawingTSSOP
PW
20
SPQ
ReelReelDiameterWidth(mm)W1(mm)330.0
16.4
A0(mm)B0(mm)K0(mm)
P1(mm)8.0
WPin1(mm)Quadrant16.0
Q1
TLC2558IPWR20006.957.11.6
PackMaterials-Page1
PACKAGEMATERIALSINFORMATION
www.ti.com
11-Mar-2008
*Alldimensionsarenominal
DeviceTLC2558IPWR
PackageType
TSSOP
PackageDrawing
PW
Pins20
SPQ2000
Length(mm)
346.0
Width(mm)346.0
Height(mm)
33.0
PackMaterials-Page2
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 MECHANICAL DATA PW (R-PDSO-G**) 14 PINS SHOWNPLASTIC SMALL-OUTLINE PACKAGE0,651480,300,190,10M0,15 NOM4,504,306,606,20Gage Plane0,251A70°–8°0,750,50Seating Plane1,20 MAX0,150,050,10PINS **DIMA MAX83,10145,10165,10206,60247,90289,80A MIN2,904,904,906,407,709,604040064/F 01/97NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion not to exceed 0,15.Falls within JEDEC MO-153POST OFFICE BOX 655303 DALLAS, TEXAS 75265•IMPORTANTNOTICE
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